this two volume set LNCS 7016 and LNCS 7017 constitutes the refereed proceedings of the 11thinternational Conference on algorithms and architectures for parallel Processing, ICA3PP 2011, held in Melbourne, Australia,...
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ISBN:
(数字)9783642246692
ISBN:
(纸本)9783642246685
this two volume set LNCS 7016 and LNCS 7017 constitutes the refereed proceedings of the 11thinternational Conference on algorithms and architectures for parallel Processing, ICA3PP 2011, held in Melbourne, Australia, in October 2011. the second volume includes 37 papers from one symposium and three workshops held together with ICA3PP 2011 main conference. these are 16 papers from the 2011internationalsymposium on Advances of Distributed Computing and Networking (ADCN 2011), 10 papers of the 4th IEEE international Workshop on Internet and Distributed Computing Systems (IDCS 2011), 7 papers belonging to the III international Workshop on Multicore and Multithreaded architectures and algorithms (M2A2 2011), as well as 4 papers of the 1st IEEE international Workshop on parallelarchitectures for Bioinformatics Systems (HardBio 2011).
Recently we proposed occam-pi as a high-level language for programming massively parallel reconfigurable architectures. the design of occam-pi incorporates ideas from CSP and pi-calculus to facilitate expressing paral...
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ISBN:
(纸本)9780769543017
Recently we proposed occam-pi as a high-level language for programming massively parallel reconfigurable architectures. the design of occam-pi incorporates ideas from CSP and pi-calculus to facilitate expressing parallelism and reconfigurability. the feasability of this approach was illustrated by building three occam-pi implementations of DCT executing on an Ambric. However, because DCT is a simple and well-studied algorithm it remained uncertain whether occam-pi would also be effective for programming novel, more complex algorithms. In this paper, we demonstrate the applicability of occam-pi for expressing various degrees of parallelism by implementing a significantly large case-study of focus criterion calculation in an autofocus algorithm on the Ambric architecture. Autofocus is a key component of synthetic aperture radar systems. Two implementations of focus criterion calculation were developed and evaluated on the basis of performance. the comparison of the performance results with a single threaded software implementation of the same algorithm show that the throughput of the two implementations are 11x and 23x higher than the sequential implementation despite a much lower (9x) clock frequency. the two designs are, respectively, 29x and 40x more energy efficient.
the proceedings contain 10 papers. the topics discussed include: floodgate: application-driven flow control in network-on-chip for manycore architectures;ROBUST: a new self-healing fault-tolerant NoC router;B2RAC: a p...
ISBN:
(纸本)9781450309479
the proceedings contain 10 papers. the topics discussed include: floodgate: application-driven flow control in network-on-chip for manycore architectures;ROBUST: a new self-healing fault-tolerant NoC router;B2RAC: a physical express link addition methodology for network on chip;BOFAR: buffer occupancy factor based adaptive router for mesh NoCs;floor-planning-aware design space exploration for application-specific hierarchical networks-on-chip;contrasting multi-synchronous MPSoC design styles for fine-grained clock domain partitioning: the full-HD video playback case study;selecting the optimal system: automated design of application-specific systems-on-chip;partitioning and mapping on NoC-based MPSoC: an energy consumption saving approach;enhancing the security of time-division-multiplexing networks-on-chip through the use of multipath routing;and dynamic clustering for distinct parallelprogramming models on NoC-based MPSoCs.
this paper investigates the impact of dynamic clustering and the use of hardware support for distinct parallelprogramming models in an NoC-based MPSoC environment. Using a dynamically adaptable hardware, the platform...
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Game developers are often faced with very demanding requirements on huge numbers of agents moving naturally through increasingly large and detailed virtual worlds. Withthe advent of multi-core architectures, new appr...
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the solution of large sparse network equations is a recurrent problem in almost every algorithm of power system simulation, which is widely used in offline analysis, online stability assessment and control. Nowadays, ...
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In this paper we present the design and implementation of TMbox: An MPSoC built to explore trade-offs in multicore design space and to evaluate parallelprogramming proposals such as Transactional Memory (TM). Our fle...
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ISBN:
(纸本)9780769543017
In this paper we present the design and implementation of TMbox: An MPSoC built to explore trade-offs in multicore design space and to evaluate parallelprogramming proposals such as Transactional Memory (TM). Our flexible system, comprised of MIPS R3000-compatible cores is easily modifiable to study different architecture, library and operating system extensions. For this paper we evaluate a 16-core Hybrid Transactional Memory implementation based on the TinySTM-ASF proposal on a Virtex-5 FPGA and we accelerate three benchmarks written to investigate TM.
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