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2012 international conference on reconfigurable computing and fpgas, reconfig 2012

ISBN: (纸本)9781467329217

The proceedings contain 65 papers. The topics discussed include: an efficient and scalable architecture for real-time distortion removal and rectification of live camera images;power-efficient and scalable virtual router architecture on FPGA;a high-performance reconfigurable computing architecture using a magnetic configuration memory;static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices;exploring hardware work queue support for lightweight threads in MPSOCs;a lightweight speculative and predicative scheme for hardware execution;optimizing inter-FPGA communication by automatic cannel adaptation;an automated test framework for experimenting with stochastic behavior in reconfigurable logic;multi-FPGA prototyping environment: large benchmark generation and signals routing;and compact Trie forest: scalable architecture for IP lookup on fpgas.

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Selected Papers from the international conference on reconfigurable computing and fpgas (reconfig'10)

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international JOURNAL OF reconfigurable computing 2012年第unknown期2012卷

作者： Feregrino, Claudia Arias, Miguel Gaj, Kris Prasanna, Viktor K. Santambrogio, Marco D. Sass, Ron Inst Nacl Astrofis Opt & Electr Puebla 72840 Mexico George Mason Univ Fairfax VA 22030 USA Univ Southern Calif Los Angeles CA 90033 USA Politecn Milan I-20133 Milan Italy Univ N Carolina Charlotte NC 28223 USA

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A Model Design of a 2560-Channel Neural Spike Detection Platform

A Model Design of a 2560-Channel Neural Spike Detection Plat...

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international conference on reconfigurable computing and fpgas (reconfig)

作者： Elaraby, Nashwa Obeid, Iyad Temple Univ Dept Elect & Comp Engn Philadelphia PA 19122 USA

ISBN: (纸本)9781467329194;9781467329200

A model design of a 2560-channel neural signal processing platform is presented. The design carries out spike detection over a large reconfigurable number of channels on Field Programmable Gate Arrays (fpgas), and integrates the application of high-speed serial transceivers to allow for the required massive input data transmissions.

关键词： reconfigurable FPGA neural spike detection high-speed serial transceivers

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A High-Performance reconfigurable computing Architecture using a Magnetic Configuration Memory

A High-Performance Reconfigurable Computing Architecture usi...

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international conference on reconfigurable computing and fpgas (reconfig)

作者： Silva, Victor Fernandes, Jorge R. Vestias, Mario P. Neto, Horacio C. INESC ID IST UTL Lisbon Portugal

ISBN: (纸本)9781467329194;9781467329200

This paper presents a new architecture for a coarse-grained reconfigurable array targeted to linear algebra problems. The reconfiguration memories are implemented using magnetic tunneling junctions. These storage elements provide for non-volatility and for a very effective implementation of multi-context planes. The proposed architecture is organized as a 2-dimensional mesh of double precision floating-point execution units. The execution units are run-time reconfigurable. Its configuration information defines the operation to be executed and the data flow intra and inter execution units. The synthesis results of a prototype design of a 4x4 array targeting a 65 nm CMOS technology confirm that the proposed architecture is able to provide a very significant computational density and that the magnetic-based configuration memory can provide a very area efficient run-time reconfigurability.

关键词： High-Performance reconfigurable computing Coarse Grain reconfigurable Arrays Linear Algebra Double Precision Floating Point

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Evaluating reconfigurable Dataflow computing Using the Himeno Benchmark

Evaluating Reconfigurable Dataflow Computing Using the Himen...

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international conference on reconfigurable computing and fpgas (reconfig)

作者： Sato, Yukinori Inoguchi, Yasushi Luk, Wayne Nakamura, Tadao Research Center for Advanced Computing Infrastructure JAIST Japan

ISBN: (纸本)9781467329194;9781467329200

Heterogeneous computing using FPGA accelerators is a promising approach to boost the performance of application programs within given power consumption. This paper focuses on optimizations targeting FPGA-based reconfigurable dataflow computing platform, and shows how they benefit an application. In order to evaluate them, we use the Himeno benchmark, which is a floating point computation kernel known to be bound by memory bandwidth. To understand the performance characteristics of the benchmark, we compare it with the current state-of-the-art implementation on GPUs. From the results, we find that our implementation with specialized dataflow pipelines outperforms the current state-of-the-art GPU implementations by making full use of memory locality.

关键词： data flow BENCHMARKS performance characteristics current status memory bandwidth configurability Power consumption

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Static Voltage Over-scaling and Dynamic Voltage Variation Tolerance with Replica Circuits and Time Redundancy in reconfigurable Devices

Static Voltage Over-scaling and Dynamic Voltage Variation To...

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international conference on reconfigurable computing and fpgas (reconfig)

作者： Alnajjar, Dawood Hashimoto, Masanori Onoye, Takao Mitsuyama, Yukio Osaka Univ Dept Informat Syst Engn Osaka Japan

ISBN: (纸本)9781467329194;9781467329200

This paper studies performance and timing failure probability of time-shifted redundant circuits and replica circuits. Measurement-based experiments using a fabricated test chip are performed. For an approximately similar false positive error probability for time-shifted redundant circuits and replica circuits, the false negative error probability of time-shifted redundant circuits is approximately two orders of magnitude less than that of the replica circuits. When attaining a false negative error of zero, time-shifted redundant circuits achieves one order of magnitude less in false positive error probability than that of the replica circuits.

关键词： Dynamic voltage variations voltage scaling replica circuits time diversity timing errors error prediction error detection variation tolerant circuits

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An Automated Test Framework for Experimenting with Stochastic Behavior in reconfigurable Logic

An Automated Test Framework for Experimenting with Stochasti...

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international conference on reconfigurable computing and fpgas (reconfig)

作者： Birklykke, Alex Aa Le Moullec, Yannick Alminde, Lars K. Prasad, Ramjee Aalborg Univ Dept Elect Syst DK-9220 Aalborg O Denmark

ISBN: (纸本)9781467329194;9781467329200

In this paper, we present an automated test framework for the characterization of stochastic behavior in logic circuits. The framework is intended as a platform for experimenting with and providing statistics on digital architectures given behavioral uncertainties at the gate-level. As an experimental platform, we propose to use an FPGA due to the proven value of reconfigurable architectures in design space exploration. We hypothesize that stochastic behavior can be introduced in fpgas using external noise sources;a fact that is later confirmed by characterizing the behavior of an FPGA IO block subject to voltage/frequency scaling and V-dd-noise. The framework provides easy interfacing with laboratory equipment, design of experiment capabilities and automatic test execution, thus providing a powerful tool for characterizing stochastic behavior in reconfigurable logic.

关键词： random behavior reconfigurable logic Field programmable gate arrays Frameworks Automatic testing reconfigurable architectures Space Exploration Automation

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A Case Study of Streaming Storage Format for Sparse Matrices

A Case Study of Streaming Storage Format for Sparse Matrices

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international conference on reconfigurable computing and fpgas (reconfig)

作者： Jain-Mendon, Shweta Sass, Ron Univ N Carolina Reconfigurable Comp Syst Lab Charlotte NC 28223 USA

ISBN: (纸本)9781467329194;9781467329200

The Field-Programmable Gate Array is an excellent match for the sparse matrix-vector multiply operation because of its enormous computational capacity and its ability to build a custom memory hierarchy that matches the memory access patterns of the operation. This paper describes a streaming sparse matrix format and a custom memory subsystem that decodes it on-the-fly for multiple compute units. Results show that the proposed design is very efficient and allows the sparse matrix to be streamed sequentially from off-chip RAM. On a Xilinx Virtex-4 device, this results in an average of 58% memorybandwidth efficiency for one compute unit and 70% memorybandwidth efficiency for two compute units. The design is capable of achieving an average of 47% of theoretical peak floating-point performance for each compute unit.

关键词： Sparse Matrix Storage Formats

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Exploring Hardware Work Queue Support for Lightweight Threads in MPSoCs

Exploring Hardware Work Queue Support for Lightweight Thread...

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international conference on reconfigurable computing and fpgas (reconfig)

作者： Sharma, Rahul R. Rajasekhar, Yamuna Sass, Ron Univ N Carolina Reconfigurable Comp Syst Lab Charlotte NC 28223 USA

ISBN: (纸本)9781467329194;9781467329200

Fine-grain thread parallelism using task based programming models are a new trend in achieving massively parallel computations. Often, software pre-fetching and queuing mechanisms for managing these dynamic environments are inadequate, failing to keep the processor cores busy with computation. At the same time, the CPU-memory performance gap is getting worse and this puts a strain on memory subsystem to keep cores in a busy state. We describe a hardware based pre-fetching and queuing mechanism aimed at assisting the over-subscription of very lightweight threads per core. Experiments with a soft processor and a reconfigurable accelerator core are reported. The hardware demonstrates the ability to block on out-of-order memory transactions and alleviates the software bottleneck.

关键词： Computer hardware multiprocessor system on chip THREADS core Queue Lightweight Queuing Mechanism Processor Core PROCESSOR

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Design and Analysis of Layered Coarse-Grained reconfigurable Architecture

Design and Analysis of Layered Coarse-Grained Reconfigurable...

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international conference on reconfigurable computing and fpgas (reconfig)

作者： Rakossy, Zoltan Endre Naphade, Tejas Chattopadhyay, Anupam Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst ICE Aachen Germany

ISBN: (纸本)9781467329194;9781467329200

Coarse-grained reconfigurable architectures (CGRAs) represent an important class of programmable accelerators with a significant performance advantage for data-driven, systolic algorithms. In this paper, we present a novel CGRA where data access, data transport and execution are separately layered into dedicated, independent structures. The proposed architecture concept allows for independent control and optimization on each layer to address the storage access bottleneck, faced by state-of-the-art CGRAs. The architecture is programmable and the implementation is derived from a high-level language specification, allowing fast design exploration, debugging and simulation. Up to 50% run-time performance improvement and 5x area-time-energy product gain of the layered CGRA over a non-layered one is demonstrated with 2 case studies from demanding linear algebra applications.

关键词： Coarse-Grained reconfigurable Architecture (CGRA) LU decomposition Matrix Multiplication Layered Architecture

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