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检索条件"任意字段=2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2012"

共 79 条记录，以下是31-40 订阅

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Architecture and applications for an all-FPGA parallel computer

Architecture and applications for an all-FPGA parallel compu...

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41st international conference on Parallel Processing Workshops, ICPPW 2012

作者： Rajasekhar, Yamuna Sass, Ron Reconfigurable Computing Systems Lab. University of North Carolina at Charlotte Charlotte NC United States

ISBN: (纸本)9780769547954

The reconfigurable computing Cluster (RCC) project has been investigating unconventional architectures for high end computing using a cluster of FPGA devices connected by a high-speed, custom network. Most applications use the fpgas to realize an embedded System-on-a-Chip (SoC) design augmented with application-specific accelerators to form a message-passing parallel computer. Other applications take a single accelerator core and tessellate the core across all of the devices, treating them like a large virtual FPGA. The experimental hardware has also been used for basic computer research by emulating novel architectures. This article discusses the genesis of the over-arching project, summarizes results of individual investigations that have been completed, and how this approach may prove useful in the investigation of future Exascale systems. © 2012 IEEE.

关键词： Field programmable gate arrays (FPGA)

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An overview of Selected Hybrid and reconfigurable Architectures

An overview of Selected Hybrid and Reconfigurable Architectu...

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IEEE international conference on Industrial Technology (ICIT)

作者： Stojanovic, Sasa Bojic, Dragan Bojovic, Miroslav Valero, Mateo Milutinovic, Veljko Univ Belgrade Belgrade 11001 Serbia Tech Univ Catalonia Barcelona Spain

ISBN: (纸本)9781467303422

Node level heterogeneous architectures have become attractive during the last decade for several reasons: Compared to traditional symmetric CPUs, they offer high real-application performance and can be energy and/or cost efficient. In this paper, we give an overview of the state-of-the-art in heterogeneous computing, focusing on commonly found architectures: The Cell Broadband Engine Architecture (CBEA), NVidia graphics processing units (GPUs), and field programmable gate arrays (fpgas) accelerators solutions from Maxeler MaxNodes (MAX) and SGI systems (RASC). We present a review of hardware, available software tools for each solution, a quantitative and a qualitative comparison of the architectures, and give our view on the future of heterogeneous computing.

关键词： reconfigurable architectures ARCHITECTURE Field programmable gate arrays Building construction

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Evaluating reconfigurable dataflow computing using the Himeno benchmark

Evaluating reconfigurable dataflow computing using the Himen...

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international conference on reconfigurable computing and fpgas (reconfig)

作者： Yukinori Sato Yasushi Inoguchi Wayne Luk Tadao Nakamura JST CREST Japan Research Center for Advanced Computing Infrastructure JAIST Japan Department of Computing Imperial College London UK Department of Information and Computer Science Keio University Japan

Heterogeneous computing using FPGA accelerators is a promising approach to boost the performance of application programs within given power consumption. This paper focuses on optimizations targeting FPGA-based reconfigurable dataflow computing platform, and shows how they benefit an application. In order to evaluate them, we use the Himeno benchmark, which is a floating point computation kernel known to be bound by memory bandwidth. To understand the performance characteristics of the benchmark, we compare it with the current state-of-the-art implementation on GPUs. From the results, we find that our implementation with specialized dataflow pipelines outperforms the current state-of-the-art GPU implementations by making full use of memory locality.

关键词： Kernel Field programmable gate arrays Benchmark testing Optimization Bandwidth Engines Memory management

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Exploring hardware work queue support for lightweight threads in MPSoCs

Exploring hardware work queue support for lightweight thread...

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international conference on reconfigurable computing and fpgas (reconfig)

作者： Rahul R Sharma Yamuna Rajasekhar Ron Sass Reconfigurable Computing Systems Laboratory University of North Carolina Charlotte USA

Fine-grain thread parallelism using task based programming models are a new trend in achieving massively parallel computations. Often, software pre-fetching and queuing mechanisms for managing these dynamic environments are inadequate, failing to keep the processor cores busy with computation. At the same time, the CPU-memory performance gap is getting worse and this puts a strain on memory subsystem to keep cores in a busy state. We describe a hardware based pre-fetching and queuing mechanism aimed at assisting the over-subscription of very lightweight threads per core. Experiments with a soft processor and a reconfigurable accelerator core are reported. The hardware demonstrates the ability to block on out-of-order memory transactions and alleviates the software bottleneck.

关键词： Instruction sets Hardware Throughput Registers Random access memory Switches Memory management

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A multi-core FPGA-based SoC architecture with domain segregation

A multi-core FPGA-based SoC architecture with domain segrega...

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international conference on reconfigurable computing and fpgas (reconfig)

作者： Daniel Kliem Sven-Ole Voigt Institute for Reliable Computing Hamburg University of Technology Hamburg Germany

Nowadays, fpgas are sufficiently large to host not only single soft-core CPUs but a whole Multi-Processor System-on-a-Chip (MPSoC). They follow the recent trend of chip-multiprocessing. Given the requirement for domain segregation in safety and security related applications, we propose an FPGA-based architecture that achieves segregation by secure bus bridges. According to the SoC-paradigm, we use a single shared memory controller to reduce external component count. We pay special attention to performance evaluation and avoidance of temporal conflicts. The architecture is evaluated by dedicated bus observers using simulation and hardware prototypes and is finally benchmarked by running multiple isolated off-the-shelf Linux systems.

关键词： Bridges System-on-a-chip Radiation detectors Benchmark testing Field programmable gate arrays Clocks Computer architecture

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An automated test framework for experimenting with stochastic behavior in reconfigurable logic

An automated test framework for experimenting with stochasti...

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international conference on reconfigurable computing and fpgas (reconfig)

作者： Alex Aa. Birklykke Yannick Le Moullec Lars K. Alminde Ramjee Prasad Department of Electronic Systems Aalborg University Aalborg Ø Denmark GomSpace APS Niels Jernes Vej 10 DK-9220 Aalborg Ø

In this paper, we present an automated test framework for the characterization of stochastic behavior in logic circuits. The framework is intended as a platform for experimenting with and providing statistics on digital architectures given behavioral uncertainties at the gate-level. As an experimental platform, we propose to use an FPGA due to the proven value of reconfigurable architectures in design space exploration. We hypothesize that stochastic behavior can be introduced in fpgas using external noise sources; a fact that is later confirmed by characterizing the behavior of an FPGA IO block subject to voltage/frequency scaling and V dd -noise. The framework provides easy interfacing with laboratory equipment, design of experiment capabilities and automatic test execution, thus providing a powerful tool for characterizing stochastic behavior in reconfigurable logic.

关键词： Field programmable gate arrays Uncertainty Vectors Timing Clocks Noise Software

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A reconfigurable computing Approach for Efficient and Scalable Parallel Graph Exploration

A Reconfigurable Computing Approach for Efficient and Scalab...

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23rd IEEE international conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Betkaoui, Brahim Wang, Yu Thomas, David B. Luk, Wayne Univ London Imperial Coll Sci Technol & Med Dept Comp London England Tsinghua Univ Dept Elect Engn Tsinghua Natl Lab Informat Sci & Technol Beijing Peoples R China Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London England

ISBN: (纸本)9780769547688

In many application domains, data are represented using large graphs involving millions of vertices and billions of edges. Graph exploration algorithms, such as breadth-first search (BFS), are largely dominated by memory latency and are challenging to process efficiently. In this paper, we present a reconfigurable hardware methodology for efficient parallel processing of large-scale graph exploration problems. Our methodology is based on a reconfigurable hardware architecture which decouples computation and communication while keeping multiple memory requests in flight at any given time, taking advantage of the hardware capabilities of both fpgas and the parallel memory subsystem. To validate our methodology, we provide a detailed design description of the Breadth-First Search algorithm on an FPGA-based high performance computing system. Using graph data based on the power-law graphs found in real-word problems, we are able to achieve performance results that are superior to those of high performance multi-core systems in the recent literature for large graph instances, and a throughput in excess of 2.5 billion traversed edges per second on RMAT graphs with 16 million vertices and over a billion edges. Using four Virtex-5 LX330 fpgas based on 65nm technology and running at 75MHz, our BFS design achieves more than twice the speed of a 32-core Xeon X7560 based on 45nm technology and running at 2.26GHz.

关键词： Line graph memory latency breadth first search Exploration graph data reconfigurable hardware PARALLEL PROCESSING (COMPUTERS) Running Power law

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Static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices

Static voltage over-scaling and dynamic voltage variation to...

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international conference on reconfigurable computing and fpgas (reconfig)

作者： Dawood Alnajjar Masanori Hashimoto Takao Onoye Yukio Mitsuyama Department of Information Systems Engineering Osaka University and JST CREST Osaka Japan School of Systems Engineering Kochi University of Technology and JST CREST Kochi Japan

This paper studies performance and timing failure probability of time-shifted redundant circuits and replica circuits. Measurement-based experiments using a fabricated test chip are performed. For an approximately similar false positive error probability for time-shifted redundant circuits and replica circuits, the false negative error probability of time-shifted redundant circuits is approximately two orders of magnitude less than that of the replica circuits. When attaining a false negative error of zero, time-shifted redundant circuits achieves one order of magnitude less in false positive error probability than that of the replica circuits.

关键词： Finite impulse response filter Delay Redundancy Field programmable gate arrays Computer architecture Noise

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A case study of streaming storage format for sparse matrices

A case study of streaming storage format for sparse matrices

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international conference on reconfigurable computing and fpgas (reconfig)

作者： Shweta Jain-Mendon Ron Sass Reconfigurable Computing Systems Laboratory University of North Carolina Charlotte USA

The Field-Programmable Gate Array is an excellent match for the sparse matrix-vector multiply operation because of its enormous computational capacity and its ability to build a custom memory hierarchy that matches the memory access patterns of the operation. This paper describes a streaming sparse matrix format and a custom memory subsystem that decodes it on-the-fly for multiple compute units. Results show that the proposed design is very efficient and allows the sparse matrix to be streamed sequentially from off-chip RAM. On a Xilinx Virtex-4 device, this results in an average of 58% memory-bandwidth efficiency for one compute unit and 70% memory-bandwidth efficiency for two compute units. The design is capable of achieving an average of 47% of theoretical peak floating-point performance for each compute unit.

关键词： Indexes Sparse matrices Bandwidth Vectors Performance evaluation Finite element methods Decoding

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Design and analysis of layered coarse-grained reconfigurable architecture

Design and analysis of layered coarse-grained reconfigurable...

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international conference on reconfigurable computing and fpgas (reconfig)

作者： Zoltán Endre Rákossy Tejas Naphade Anupam Chattopadhyay Institute for Communication Technologies and Embedded Systems (ICE) RWTH Aachen University Germany Department of Electrical Engineering Indian Institute of Technology Bombay India

Coarse-grained reconfigurable architectures (CGRAs) represent an important class of programmable accelerators with a significant performance advantage for data-driven, systolic algorithms. In this paper, we present a novel CGRA where data access, data transport and execution are separately layered into dedicated, independent structures. The proposed architecture concept allows for independent control and optimization on each layer to address the storage access bottleneck, faced by state-of-the-art CGRAs. The architecture is programmable and the implementation is derived from a high-level language specification, allowing fast design exploration, debugging and simulation. Up to 50% run-time performance improvement and 5× area-time-energy product gain of the layered CGRA over a non-layered one is demonstrated with 2 case studies from demanding linear algebra applications.

关键词： Registers Arrays Pipelines Assembly Bandwidth Timing

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