The proceedings contain 136 papers. The topics discussed include: FPGA implementation of hierarchical enumerative coding for locally stationary image source;efficient floating-point polynomial evaluation on FPGAs;iter...
ISBN:
(纸本)9781479900046
The proceedings contain 136 papers. The topics discussed include: FPGA implementation of hierarchical enumerative coding for locally stationary image source;efficient floating-point polynomial evaluation on FPGAs;iterative floating point computation using FPGA DSP blocks;scalable and high throughput biosensing platform;a FPGA design for high speed feature extraction from a compressed measurement stream;FPGA based rekeying for cryptographic key management in storage area network;managing the FPGA memory wall: custom computing or vector processing?;token-based dictionary pattern matching for text analytics;accelerated FPGA repair through shifted scrubbing;TPUTCACHE: high-frequency, multi-way cache for high-throughput FPGA applications;low-cost, high-performance branch predictors for soft processors;hardware-accelerated regular expression matching for high-throughput text analytics;and rapid FPGA design prototyping through preservation of system logic: a case study.
""The unique promise of embedded systems in FPGAs is that designers can develop and modify their own peripheral hardware with a high degree of flexibility. However, the task of verifying the hardware commonl...
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ISBN:
(纸本)9781479900046
""The unique promise of embedded systems in FPGAs is that designers can develop and modify their own peripheral hardware with a high degree of flexibility. However, the task of verifying the hardware commonly involves writing software to interact with it. T""
""The herein presented research is motivated by the need for reconfigurable, flexible computing arrays targeted at streaming applications that contain a large degree of instruction-level parallelism. Such ar...
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ISBN:
(纸本)9781479900046
""The herein presented research is motivated by the need for reconfigurable, flexible computing arrays targeted at streaming applications that contain a large degree of instruction-level parallelism. Such arrays are usually referred to as coarse-grained rec""
""Ibex [1] is a novel database storage engine featuring hybrid, FPGA-accelerated query processing. The first prototype of Ibex has been implemented within the open-source MySQL database. In Ibex, an FPGA is ...
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ISBN:
(纸本)9781479900046
""Ibex [1] is a novel database storage engine featuring hybrid, FPGA-accelerated query processing. The first prototype of Ibex has been implemented within the open-source MySQL database. In Ibex, an FPGA is inserted into the data path between disk and CPU t""
This paper presents an alternative FPGA design compilation flow that reduces the back-end time required to implement a design. Beginning with the GReasy front-end and proceeding through the TFlow back-end, this flow c...
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ISBN:
(纸本)9781479900046
This paper presents an alternative FPGA design compilation flow that reduces the back-end time required to implement a design. Beginning with the GReasy front-end and proceeding through the TFlow back-end, this flow consists of a rapid method for design assembly, decoupled from the vendor tools. This enables software-like turnaround time for faster prototyping and increased productivity.
""We will demonstrate a portable FPGA tablet running a spiking neural network for handwriting recognition. The user draws digits on the tablet's touch-screen, and the neural network performs digit recogn...
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ISBN:
(纸本)9781479900046
""We will demonstrate a portable FPGA tablet running a spiking neural network for handwriting recognition. The user draws digits on the tablet's touch-screen, and the neural network performs digit recognition.""
Realistic benchmarks are important for FPGA Architecture and CAD evaluation. This paper provides a demo illustrating how designs described in HDL can be converted to BLIF using the Titan flow, and used in academic CAD...
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ISBN:
(纸本)9781479900046
Realistic benchmarks are important for FPGA Architecture and CAD evaluation. This paper provides a demo illustrating how designs described in HDL can be converted to BLIF using the Titan flow, and used in academic CAD tools.
Large digital signal processing applications like particle filtering require a tradeoff between execution time and area in order to scale on FPGAs. This research focuses on developing a methodology to make this tradeo...
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ISBN:
(纸本)9781479900046
Large digital signal processing applications like particle filtering require a tradeoff between execution time and area in order to scale on FPGAs. This research focuses on developing a methodology to make this tradeoff based on structure in the mathematical description of the application. Structure is expressed using higher-order functions which are transformed using tradeoff rules to reduce area usage on FPGA.
In this manuscript, we have explored how the use of DSP blocks in the implementation of two authenticated-encryption modes of AES can optimize the PAR figures. Our results reflect that a 20.98 % reduction in slice uti...
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ISBN:
(纸本)9781479900046
In this manuscript, we have explored how the use of DSP blocks in the implementation of two authenticated-encryption modes of AES can optimize the PAR figures. Our results reflect that a 20.98 % reduction in slice utilization can be achieved at a throughput higher than 25 Mbps (12 MHz) in the Artix-7 XC7A200TL FPGA.
The conventional matrix multiplication algorithms that are suitable for dense matrices do not perform well on the corresponding Sparse Matrix-Matrix Multiplication (SMMM) operation. In particular, they do not utilize ...
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ISBN:
(纸本)9781479900046
The conventional matrix multiplication algorithms that are suitable for dense matrices do not perform well on the corresponding Sparse Matrix-Matrix Multiplication (SMMM) operation. In particular, they do not utilize the sparsity of the matrix. This paper describes a new technique for performing the SMMM operation using a novel storage format for sparse matrices. To demonstrate the feasibility of this technique, the SMMM operation is implemented on an FPGA and various parameters that affect the performance of the design are explored.
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