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检索条件"任意字段=2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013"

共 228 条记录，以下是91-100 订阅

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SDR Control Interface: An FPGA based infrastructure for control of VPX Software Defined Radio systems

SDR Control Interface: An FPGA based infrastructure for cont...

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23rd international conference on field programmable logic and applications (fpl)

作者： Castillo, Stefanie Astarloa, Armando Lazaro, Jesus Salas, Sergio Ballesteros, Isaac Univ Basque Country Bilbao Spain SystemonChip Engn Zitek Bilbao ETSI Bilbao 48013 Spain iQUBE Res Vigo 36310 Spain

ISBN: (纸本)9781479900046

We present a flexible, scalable, re-usable, opensource based control and Built-In Self-Test (BIST) System-onprogrammable- Chip (SoPC) hardware infrastructure: the Software Defined Radio (SDR) control interface. Our design endows centralized Virtual Path cross-connect (VPX) switch fabric systems with a hardware infrastructure to control and test the RF Transceiver (TRX) Integrated Circuits (ICs) of a SDR platform. We include a detailed description of the design, show results of an FPGA based implementation and finally experimental validation of the system is carried out by successfully configuring and controlling the Texas Instruments (TI) TRX SDR ICs.

关键词： built-in self test field programmable gate arrays integrated circuit testing radio transceivers radiofrequency integrated circuits software radio system-on-chip

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A LOW-COMPLEXITY IMPLEMENTATION OF QC-LDPC ENCODER IN RECONFIGURABLE logic

A LOW-COMPLEXITY IMPLEMENTATION OF QC-LDPC ENCODER IN RECONF...

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23rd international conference on field programmable logic and applications (fpl)

作者： Tzimpragos, Georgios Kachris, Christoforos Soudris, Dimitrios Tomkos, Ioannis Natl Tech Univ Athens 15780 Zographou Campus Athens Greece Athens Informat Technol Athens 19002 Greece

ISBN: (纸本)9781479900046

Low Density Parity Check(LDPC) codes are a special class of error correction codes widely used in communication and disk storage systems, due to their Shannon limit approaching performance and their favorable structure. In this paper, a methodology for optimized hardware multiplication by constant matrices in GF(2) is introduced and then applied to the Quasi-Cyclic LDPC encoding algorithm. Taking advantage of the fact that the parity check matrix rarely changes, the signals in many cases are hard-wired into the LUTs and thus the cyclic-shifters and blockmemories conventionally used are eliminated. Therefore, the proposed framework leads to less complex, mapped to reconfigurable logic designs, whereas it combines the performance of hard-wired solutions (high throughput, low latency) and the flexibility of the software and its hardware counterparts. These advantages in terms of hardware savings and throughput prove that the proposed encoder scheme is suitable for high-speed applications, such as long-haul optical transmission, where speed and resources utilization are a major issue.

关键词： codecs cyclic codes error correction codes parity check codes

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FPGA IMPLEMENTATION OF HIERARCHICAL ENUMERATIVE CODING FOR LOCALLY STATIONARY IMAGE SOURCE

FPGA IMPLEMENTATION OF HIERARCHICAL ENUMERATIVE CODING FOR L...

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23rd international conference on field programmable logic and applications (fpl)

作者： Bai, Yuhui Ahmed, Syed Zahid Granado, Bertrand Univ Cergy Pontoise CNRS ENSEA ETIS Cergy France Univ Paris 06 CNRS LIP6 F-75252 Paris 05 France

ISBN: (纸本)9781479900046

In this paper we present a novel high performance, low resource utilization and power efficient hardware architecture of an entropy coding scheme. The proposed architecture implements the Hierarchical Enumerative Coding algorithm (HENUC) on an embedded soft-processor based System-on-Chip, in which HENUC is an integral part of a wavelet based encoder oriented for locally stationary image source. Though HENUC has been implemented on an embedded DSP architecture before, the throughput was low. This paper proposes an optimized parallel architecture for HENUC, which is validated on a Terasic DE4-230 board containing Altera Stratix IV FPGA. Our implementation at 100MHz provides 5.7x speedup over Intel Xeon 8-core CPU and 12.3x speedup over TI DSP for 512 x 512 image while consuming less than 500 mw FPGA core power.

关键词： digital signal processing chips embedded systems entropy codes field programmable gate arrays image coding parallel architectures system-on-chip

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ANALYZING THE THERMAL HOTSPOTS IN FPGA-BASED EMBEDDED SYSTEMS

ANALYZING THE THERMAL HOTSPOTS IN FPGA-BASED EMBEDDED SYSTEM...

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23rd international conference on field programmable logic and applications (fpl)

作者： Amrouch, Hussam Ebi, Thomas Schneider, Josef Parameswaran, Sridevan Henkel, Joerg Karlsruhe Inst Technol D-76021 Karlsruhe Germany Univ New South Wales Sydney NSW 2052 Australia

ISBN: (纸本)9781479900046

The rapid push towards the minimization of the feature sizes of the process technology nodes in the nano-CMOS era has significantly increased the power densities and made State-of-the-Art FPGAs vulnerable to diverse problems induced by excessive temperatures. As a result, there is a prominent need to accurately study the FPGA thermal characteristics. Our experimental setup employs a thermal camera that captures the infrared emissions from the silicon wafer of an FPGA die allowing us to evaluate the accuracy of the methods conventionally used for thermal analysis, such as thermal simulations. Based on our observation that the memory interface is the thermal hotspot of an FPGA-based embedded system, we demonstrate that the cache plays a dominant thermal role by reducing memory accesses;we carefully examine the influence of various cache parameters on the FPGA temperature and propose a model linking these quantities, with an average maximum error of only 0.64 degrees C.

关键词： CMOS integrated circuits elemental semiconductors embedded systems field programmable gate arrays silicon thermal analysis

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A HIGH-PERFORMANCE OVERLAY ARCHITECTURE FOR PIPELINED EXECUTION OF DATA FLOW GRAPHS

A HIGH-PERFORMANCE OVERLAY ARCHITECTURE FOR PIPELINED EXECUT...

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23rd international conference on field programmable logic and applications (fpl)

作者： Capalija, Davor Abdelrahman, Tarek S. Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 1A1 Canada

ISBN: (纸本)9781479900046

A major issue facing the widespread use of FPGAs as accelerators is their programmability wall: the difficulty of hardware design and the long synthesis times. Overlays-presynthesized FPGA circuits that are themselves reconfigurable-promise to tackle these challenges. We design and evaluate an overlay architecture, structured as a mesh of functional units, for pipelined execution of data-flow graphs (DFGs), a common abstraction for expressing parallelism in applications. We use data-driven execution based on elastic pipelines to balance pipeline latencies and achieve a high integral MAX, scalability and maximum throughput. We prototype two overlays on a Stratix IV FPGA: a 355 MHz 24x16 integer overlay and a 312 MHz 18x16 floating-point overlay. We also design a tool that maps DFGs to overlays. We map 15 DFGs and show that the two overlays deliver throughputs of up to 35 GOPS and 22 GFLOPS, respectively. We also show that DFG mapping is fast, taking no more than 6 seconds for the largest DFG. Thus, our overlay architecture raises the level of abstraction of FPGA programming closer to that of software and avoids lengthy synthesis time, easing the use of these devices to accelerate applications.

关键词： field programmable gate arrays flow graphs logic design pipeline processing

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AREA/PERFORMANCE EVALUATION OF DIGIT-DIGIT GF(2^K) MULTIPLIERS ON FPGAS

AREA/PERFORMANCE EVALUATION OF <i>DIGIT-DIGIT</i> GF(2<i><SU...

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23rd international conference on field programmable logic and applications (fpl)

作者： Morales-Sandoval, Miguel Diaz-Perez, Arturo Cinvestav Tamaulipas Informat Technol Lab Natl Polytech Inst Res Ctr Adv Studies Cd Victoria Mexico

ISBN: (纸本)9781479900046

This work describes novel hardware architectures for GF(2(k)) multipliers using a digit-digit approach. Contrary to the bit-serial and digit-serial approaches previously addressed in the literature, we consider the partition of the multiplier, multiplicand and modulus in several digits and execute a field multiplication in an iterative way, like in a software implementation but exploiting the parallelism in the operations. We focused on parametric designs that allow to study area-performance trade offs when the multipliers are implemented in FPGAs. This study would guide a designer to select the most appropriate configuration based on the digits sizes in order to meet system requirements such as available resources, throughput, and efficiency. Although the proposed multiplier can be implemented for any finite field of order k, we provide implementation results for GF(2(163)) and GF(2(233)), two recommended finite fields for elliptic curve cryptography. For specific digit sizes, our proposed digit-digit multiplier uses considerably less area than a bit-serial multiplier with a penalization in the timing. Compared to a digit-serial implementation, area resources can be saved with still an improvement in the timing respect to a bit-serial implementation.

关键词： field programmable gate arrays iterative methods logic design multiplying circuits

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WEASEL: A PLATFORM-INDEPENDENT STREAMING-OPTIMIZED SATA CONTROLLER

WEASEL: A PLATFORM-INDEPENDENT STREAMING-OPTIMIZED SATA CONT...

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23rd international conference on field programmable logic and applications (fpl)

作者： Lehmann, Patrick Frank, Thomas Knodel, Oliver Koehler, Steffen Preusser, Thomas B. Spallek, Rainer G. Tech Univ Dresden Dept Comp Sci D-01062 Dresden Germany

ISBN: (纸本)9781479900046

field-programmable Gate Arrays, which are widely used as prototyping platforms, are intruding the domain of customspecific high-performance hardware accelerators, which operate highly efficiently by exploiting bit-and word-level parallelism. One opportunity to feed these FPGA accelerators with Gbytes of data is the direct attachment of mass-storage devices through a Serial-ATA link. State-of-the-art SATA controllers are designed and optimized for microprocessor-based systems with a random memory access pattern. Our approach, named Weasel, introduces a modularized, platform-independent and streamingoptimized SATA controller, which supports link speeds up to 6 Gbit/s. We demonstrate how to customize the given ATA standard and how to design a generic interface for different vendor-specific multi-gigabit transceivers. Implementations of the platform-independent interface for the Xilinx Virtex5 and the Altera Stratix IIGX devices prove our concept. Finally, our measurements using hard-disk and solid-state drives prove a sustained throughput of 540 Mbytes/s over a SATA 6 Gbit/s link achievable. This is close to the theoretical maximum, which is constrained by the attached devices as by the speed of their flash memory.

关键词： field programmable gate arrays hardware description languages microcomputers random-access storage

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High performance FPGA object detector: Hardware prototype

High performance FPGA object detector: Hardware prototype

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2013 23rd international conference on field programmable logic and applications, fpl 2013

作者： Zemcik, Pavel Juranek, Roman Musil, Petr Musil, Martin Hradis, Michal Department of Computer Graphics and Multimedia Faculty of Information Technology Brno University of Technology Brno Czech Republic

ISBN: (纸本)9781479900046

In this demo, we introduce a novel architecture of an engine for high performance multi-scale detection of objects in videos based on WaldBoost training algorithm. The key properties of the architecture include processing of streamed data and low resource consumption. We implemented the engine in FPGA and we show that it can process 640 × 480 pixel video streams at over 160 FPS without the need of external memory. © 2013 IEEE.

关键词： field programmable gate arrays (FPGA)

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FPGA-BASED K-MEANS CLUSTERING USING TREE-BASED DATA STRUCTURES

FPGA-BASED K-MEANS CLUSTERING USING TREE-BASED DATA STRUCTUR...

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23rd international conference on field programmable logic and applications (fpl)

作者： Winterstein, Felix Bayliss, Samuel Constantinides, George A. European Space Agcy Ground Stn Syst Div Robert Bosch Str 5 D-64293 Darmstadt Germany Imperial Coll London Dept Elect & Elect Engn London SW7 2AZ England

ISBN: (纸本)9781479900046

K-means clustering is a popular technique for partitioning a data set into subsets of similar features. Due to their simple control flow and inherent fine-grain parallelism, K-means algorithms are well suited for hardware implementations, such as on field programmable gate arrays (FPGAs), to accelerate the computationally intensive calculation. However, the available hardware resources in massively parallel implementations are easily exhausted for large problem sizes. This paper presents an FPGA implementation of an efficient variant of K-means clustering which prunes the search space using a binary kd-tree data structure to reduce the computational burden. Our implementation uses on-chip dynamic memory allocation to ensure efficient use of memory resources. We describe the trade-off between data-level parallelism and search space reduction at the expense of increased control overhead. A data-sensitive analysis shows that our approach requires up to five times fewer computational FPGA resources than a conventional massively parallel implementation for the same throughput constraint.

关键词： field programmable gate arrays pattern clustering search problems storage management tree data structures

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A hardware security scheme for RRAM-based FPGA

A hardware security scheme for RRAM-based FPGA

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2013 23rd international conference on field programmable logic and applications, fpl 2013

作者： Chen, Yi-Chung Zhang, Wei Li, Hai Helen Dept. of Electrical and Computer Engineering University of Pittsburgh Pittsburgh PA United States School of Computer Engineering Nanyang Technological University Singapore Singapore

ISBN: (纸本)9781479900046

To enhance the system integrity of FPGA-based embedded systems on hardware design, we propose a hardware security scheme for nonvolatile resistive random access memory (RRAM) based FPGA, in which internal block RAM (BRAMs) are used for configuration and temporary data storage. The proposed scheme loads obfuscated configurations into nonvolatile BRAMs to protect design data from physical attacks and utilizes Chip DNA to enable logic function. © 2013 IEEE.

关键词： field programmable gate arrays (FPGA)

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