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检索条件"任意字段=2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013"

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A FLEXIBLE HASH TABLE DESIGN FOR 10GBPS KEY-VALUE STORES ON FPGAS

A FLEXIBLE HASH TABLE DESIGN FOR 10GBPS KEY-VALUE STORES ON ...

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23rd international conference on field programmable logic and applications (fpl)

作者： Istvan, Zsolt Alonso, Gustavo Blott, Michaela Vissers, Kees Swiss Fed Inst Technol Dept Comp Sci Syst Grp Zurich Switzerland Xilinx Inc Dublin Ireland Xilinx Inc San Jose CA USA

ISBN: (纸本)9781479900046

Common web infrastructure relies on distributed main memory key-value stores to reduce access load on databases, thereby improving both performance and scalability of web sites. As standard cloud servers provide sub-linear scalability and reduced power efficiency to these kinds of scale-out workloads, we have investigated a novel dataflow architecture for key-value stores with the aid of FPGAs which can deliver consistent 10Gbps throughput. In this paper, we present the design of a novel hash table which forms the centre piece of this dataflow architecture. The fully pipelined design can sustain consistent 10Gbps line-rate performance by deploying a concurrent mechanism to handle hash collisions. We address problems such as support for a broad range of key sizes without stalling the pipeline through careful matching of lookup time with packet reception time. Finally, the design is based on a scalable architecture that can be easily parametrized to work with different memory types operating at different access speeds and latencies. We deployed this hash table in a memcached prototype to index 2 million entries in 24GBytes of external DDR3 DRAM while sustaining 13 million requests per second for UDP binary encoded memcached packets which is the maximum packet rate that can be achieved with memcached on a 10Gbps link.

关键词： DRAM chips field programmable gate arrays logic design memory architecture table lookup

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RADIATION MITIGATION EFFICIENCY OF SCRUBBING ON THE FPGA BASED CBM-TOF READ-OUT CONTROLLER

RADIATION MITIGATION EFFICIENCY OF SCRUBBING ON THE FPGA BAS...

引用

23rd international conference on field programmable logic and applications (fpl)

作者： Manz, Sebastian Gebelein, Jano Oancea, Andrei Engel, Heiko Kebschull, Udo Goethe Univ Frankfurt IRI D-60325 Frankfurt Germany

ISBN: (纸本)9781479900046

Ionizing radiation can severely disturb the function of electronic devices, especially SRAM-based electronics such as field programmable Gate Arrays (FPGAs). All components which are being mounted in a radiation environment need to be qualified for use at the respective radiation level. The theory of radiation-induced equipment failures is well known and radiation mitigation techniques have been developed. However, when using commercial off-the-shelf electronics, the internal details of electronic circuits are generally not known. Therefore, the effects of radiation and the efficiency of the mitigation techniques need to be experimentally tested before the usage of the respective electronics can be approved. Here we report the result of such a test, which was carried out at the accelerator facility at Forschungszentrum Julich, Germany, in August 2012. Contrary to previous tests, our intention was not to characterize the chip's internal logic cells using a test design which optimized for this purpose. We have evaluated the efficiency of the radiation mitigation technique scrubbing on the logic of an actual operational firmware which is currently being used by the Compressed Baryonic Matter collaboration for readout of high-energy physics detector prototypes. We did not use the particle flux as reference for characterizing the efficiency, instead, we directly counted the induced upset rate in the configuration memory of a second identical device in the beam. The firmware itself was running on a Xilinx Virtex-4 FPGA operating directly in a 2 GeV proton beam at a particle rate in the order of some 10(7)s(-1)cm(-2). Scrubbing has increased the lifespan of the design by almost a factor of 50 and reduced the amount of corrupted data by a factor of 200. Considering this result we can approve the usage of an FPGA-based read-out controller for the CBM-ToF subdetector.

关键词： SRAM chips field programmable gate arrays firmware logic design logic testing radiation effects readout electronics

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ACCELERATING SOLVERS FOR GLOBAL ATMOSPHERIC EQUATIONS THROUGH MIXED-PRECISION DATA FLOWENGINE

ACCELERATING SOLVERS FOR GLOBAL ATMOSPHERIC EQUATIONS THROUG...

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23rd international conference on field programmable logic and applications (fpl)

作者： Gan, Lin Fu, Haohuan Luk, Wayne Yang, Chao Xue, Wei Huang, Xiaomeng Zhang, Youhui Yang, Guangwen Tsinghua Univ Dept Comp Sci & Technol Haidian Peoples R China Tsinghua Univ Minist Educ Ctr Earth Syst Sci Key Lab Earth Syst Modelling Haidian Peoples R China Tsinghua Natl Lab Informat Sci TN List Haidian Peoples R China Imperial Coll London Dept Comp London England Chinese Acad Sci Inst Software Beijing 100864 Peoples R China

ISBN: (纸本)9781479900046

One of the most essential and challenging components in a climate system model is the atmospheric model. To solve the multi-physical atmospheric equations, developers have to face extremely complex stencil kernels. In this paper, we propose a hybrid CPU-FPGA algorithm that applies single and multiple FPGAs to compute the upwind stencil for the global shallow water equations. Through mixed-precision arithmetic, we manage to build a fully pipelined upwind stencil design on a single FPGA, which can perform 428 floating-point and 235 fixed-point operations per cycle. The CPU-FPGA algorithm using one Virtex-6 FPGA provides 100 times speedup over a 6-core CPU and 4 times speedup over a hybrid node with 12 CPU cores and a Fermi GPU card. The algorithm using four FPGAs provides 330 times speedup over a 6-core CPU;it is also 14 times faster and 9 times more power efficient than the hybrid CPU-GPU node.

关键词： field programmable gate arrays fixed point arithmetic floating point arithmetic microprocessor chips

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FAST, FPGA-BASED RAINBOW TABLE CREATION FOR ATTACKING ENCRYPTED MOBILE COMMUNICATIONS

FAST, FPGA-BASED RAINBOW TABLE CREATION FOR ATTACKING ENCRYP...

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23rd international conference on field programmable logic and applications (fpl)

作者： Papantonakis, Panagiotis Pnevmatikatos, Dionisios Papaefstathiou, Ioannis Manifavas, Charalampos Tech Univ Crete ECE Dept Microprocessor & Hardware Lab Iraklion Greece Synelixis Solut Ltd Chalkida Greece Technol Educ Inst Crete Appl Informat & Multimedia Dept Iraklion Greece

ISBN: (纸本)9781479900046

Encryption algorithms utilized in mobile communication systems have been under attack since their introduction, and many of these attacks have been successful in practical settings. One such example, A5/1 used in GSM, was attacked using "Rainbow Tables", i. e. pre-computed tables that trade long offline computation and large storage for run-time efficiency when cracking the code. Traditionally, Rainbow Tables were used to reverse password hashes. Their application against A5/1 opened up a new domain of exploitation. In this paper, we present an FPGA-based architecture for the efficient creation of Rainbow Tables for the A5/3 block cipher that is used in 2nd and 3rd generation mobile communication systems. The overall goal is to extract the encryption key, provided we have a ciphertext block under a known plaintext attack. The presented architecture exploits the parallelism in the Rainbow Table creation process, and using a Virtext5 LX330T achieves speedups around 9x and 550x for one and 64 compute engines respectively. We show that due to the limited available memory in our experimental setup, our approach achieves high success rates for a key space reduced to 242. We then demonstrate how we can seamlessly extend the proposed architecture to efficiently create much larger Rainbow Tables for the full key-space.

关键词： 3G mobile communication cellular radio cryptography field programmable gate arrays mobile computing telecommunication security

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FPGA BASED CONTROL FOR REAL TIME SYSTEMS

FPGA BASED CONTROL FOR REAL TIME SYSTEMS

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23rd international conference on field programmable logic and applications (fpl)

作者： Fleming, Shane T. Thomas, David B. Univ London Imperial Coll Sci Technol & Med London SW7 2AZ England

ISBN: (纸本)9781479900046

Real time systems must guarantee tasks can be completed by a given deadline. Typically they are designed around the worst case execution time (WCET) of tasks in the system. In general this creates systems with excess slack compared to the average case. Since, real time systems are often embedded devices which are typically battery operated, developing systems with large amounts of slack is undesirable because more slack means more energy usage. There exist scheduling methods that try to adapt to the current environment, for example adaptive reservation scheduling, which assigns a dynamic fraction of the computational resources to each process. However these and more advanced scheduling techniques are rarely adopted in practice due to their high computational overhead. My research hypothesis is that the overheads of complex scheduling and power saving techniques in real time systems can be reduced through developing a coprocessor in the FPGA fabric. Recent developments in reconfigurable device technology include the introduction of new hybrid FPGA/CPU chips, such as the Xilinx Zynq extensible processing platform, where an ARM core is coupled to an FPGA fabric using an AXI bus. By locating the FPGA and CPU on the same die it possible to obtain low-latency powerefficient communication between user logic in the FPGA and tasks on the CPU. This paper presents my preliminary work, which uses a software application with real time deadlines, and creates a controller in the FPGA fabric to dynamically scale the operating frequency of the CPUs, while still guaranteeing that the deadlines can be met. This coprocessor is totally agnostic to the software running on the CPU and provided that some measure of slackness, which is the deadline period subtracted from the execution time, can be obtained it will be able to scale the frequency in a safe manner and reduce dynamic power consumption.

关键词： coprocessors embedded systems field programmable gate arrays low-power electronics processor scheduling reconfigurable architectures

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Degradation in FPGAs: Monitoring, modeling and mitigation (PHD forum paper: Thesis broad overview)

Degradation in FPGAs: Monitoring, modeling and mitigation (P...

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2013 23rd international conference on field programmable logic and applications, fpl 2013

作者： Amouri, Abdulazim Tahoori, Mehdi Karlsruhe Germany

ISBN: (纸本)9781479900046

The continuous shrinking of CMOS transistors in the nano-scale era poses many manufacturing and reliability challenges such as process variation, sub-threshold leakage, power dissipation, increased circuit noise sensitivity, and reliability concerns due to transient (e.g. radiation-induced soft errors) and permanent (e.g. transistor aging) failures [1, 2]. State-of-the-art FPGAs, pushed by the ever-increasing demands on higher performance and lower power, use the latest advancements in CMOS technology [3, 4], and thus they share most of these challenges. Therefore, to guarantee the required lifetime of FPGA-mapped systems in the field, proper techniques at various levels should be devised. Transistor aging, as an important factor, causes an increase in the magnitude of threshold voltage, which in turn slows down the switching speed of the transistor and leads to timing failures and faster wear-out rates [5]. To properly deal with this issue in FPGAs, it requires modeling, monitoring and mitigation at device and architecture levels as well as the tool-chain at user level. © 2013 IEEE.

关键词： field programmable gate arrays (FPGA)

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Tile-based bottom-up compilation of custom mesh-of-functional-units FPGA overlays

Tile-based bottom-up compilation of custom mesh-of-functiona...

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2013 23rd international conference on field programmable logic and applications, fpl 2013

作者： Capalija, Davor Abdelrahman, Tarek S. Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto TorontoON Canada

ISBN: (纸本)9781479900046

Mesh-of-functional-units (mesh-of-FUs) overlays can deliver high-performance because they expose the massively parallel FPGA fabric and have the ability to be customized for different applications. However, a key challenge is how to quickly compile a number of custom mesh-of-FUs overlays to FPGA fabric such that they achieve high fMAX and scale to large mesh sizes. We propose a tile-based bottom-up CAD flow that utilizes the hierarchical physical design techniques of partitioning and floorplanning. Our flow partitions the overlay circuit into tiles, groups of adjacent overlay cells, and then compiles the tiles to a rectangular coarse-grain floorplan. Independent compilation of tiles is made possible by inserting complementary elastic buffers on inter-tile paths to ensure that these paths are not a bottleneck for fMAX. As a result, an overlay can be formed by only "stitching" a set of pre-compiled *** show that compared to the flat flow, our bottom-up flow results in higher fMAX that degrades little with increasing overlay size. Further, our flow can generate a library of pre-compiled tiles that can be reused - it can stitch a set of library tiles into a new overlay in only 35 minutes. It also allows a divide-and-conquer overlay compilation flow by compiling its tiles in parallel on multiple machines.

关键词： field programmable gate arrays (FPGA)

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Efficient Deployment Schemes of Wireless Sensor Networks 23

Efficient Deployment Schemes of Wireless Sensor Networks

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23rd international conference on Computer Theory and applications, ICCTA 2013

作者： Madkour, Marwa Soliman, S.E. Dessouky, M.I. Abd El-Samie, F.E. Atomic Energy Authority Hot Labs Center Nuclear Fuel Technology Department Cairo Egypt Menoufia University Faculty of Electronic Engineering Department of Electronics and Electrical Communications Menouf32952 Egypt

ISBN: (纸本)9781479924158

Wireless sensor networks are composed of a large number of sensor nodes with limited energy resources. One critical issue in wireless sensor networks is how to gather sensed Information in an energy efficient way since the energy is limited. In order to meet useful performance guarantees, efficient energy deployment strategies should be considered. This paper compares between random sensor deployment schemes based on fuzzy logics and a fixed node deployment scheme. Simulation results show that the random deployment scheme gives a better performance compared to the fixed scheme in terms of the number of nodes required to sense event in the sensor field. © 2013 IEEE.

关键词： Fuzzy logic

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A spiking neural network on a portable FPGA tablet

A spiking neural network on a portable FPGA tablet

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international conference on field programmable logic and applications

作者： Matthew Naylor Paul J Fox A Theodore Markettos Simon W Moore Computer Laboratory University of Cambridge Cambridge UK

We will demonstrate a portable FPGA tablet running a spiking neural network for handwriting recognition. The user draws digits on the tablet's touch-screen, and the neural network performs digit recognition.

关键词： field programmable gate arrays Biological neural networks Brain modeling Computers Laboratories Educational institutions Handwriting recognition

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From Quartus to VPR: Converting HDL to BLIF with the Titan flow

From Quartus to VPR: Converting HDL to BLIF with the Titan f...

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international conference on field programmable logic and applications

作者： Kevin E. Murray Scott Whitty Suya Liu Jason Luu Vaughn Betz Department of Electrical and Computer Engineering University of Toronto ONT Canada

Realistic benchmarks are important for FPGA Architecture and CAD evaluation. This paper provides a demo illustrating how designs described in HDL can be converted to BLIF using the Titan flow, and used in academic CAD... 详细信息

关键词： Hardware design languages Design automation Cryptography field programmable gate arrays IP networks Benchmark testing Computers

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