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检索条件"任意字段=2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013"

共 228 条记录，以下是21-30 订阅

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A SCALABLE DESIGN APPROACH FOR STENCIL COMPUTATION ON RECONFIGURABLE CLUSTERS

A SCALABLE DESIGN APPROACH FOR STENCIL COMPUTATION ON RECONF...

引用

23rd international conference on field programmable logic and applications (fpl)

作者： Niu, Xinyu Coutinho, Jose G. F. Luk, Wayne Univ London Imperial Coll Sci Technol & Med Sch Engn Dept Comp London SW7 2AZ England

ISBN: (纸本)9781479900046

Stencil-based algorithms are known to be computationally intensive and used in many scientific applications. The scalability of stencil algorithms in large-scale clusters is limited by data dependency between distributed workload. This paper proposes a scalable communication model to schedule communication operations based on available resources and algorithm properties. Experimental results from the Maxeler MPC-C500 computing system with four Virtex-6 SX475T FPGAs demonstrate linear speedup.

关键词： field programmable gate arrays logic design reconfigurable architectures

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A DIGITAL ARCHITECTURE FOR REAL-TIME NONUNIFORMITY CORRECTION OF INFRARED FOCAL-PLANE ARRAYS

A DIGITAL ARCHITECTURE FOR REAL-TIME NONUNIFORMITY CORRECTIO...

引用

23rd international conference on field programmable logic and applications (fpl)

作者： Redlich, Rodolfo Figueroa, Miguel Univ Concepcion Dept Elect Engn Ctr Opt & Photon Concepcion Chile

ISBN: (纸本)9781479900046

We present a custom digital architecture that implements the Constant Range algorithm for nonuniformity correction of infrared focal plane arrays. This scene-based technique uses the statistics of the acquired video stream to compensate the gain and offset nonuniformity of the infrared imager online. We evaluate the performance of our architecture while processing raw infrared video at 60 frames per second, with a resolution of 640x480 14-bit pixels. Our implementation of the Constant Range algorithm on a Xilinx Spartan-6 LX45 FPGA uses 1.8% of logic and 26% of arithmetic resources of the chip, consuming only 29.5mW of power.

关键词： field programmable gate arrays focal planes parallel architectures video signal processing video streaming

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FPGA IMPLEMENTATION AND DPA RESISTANCE ANALYSIS OF A LIGHTWEIGHT HMAC CONSTRUCTION BASED ON PHOTON HASH FAMILY

FPGA IMPLEMENTATION AND DPA RESISTANCE ANALYSIS OF A LIGHTWE...

引用

23rd international conference on field programmable logic and applications (fpl)

作者： Eiroa, Susana Baturone, Iluminada Univ Seville Dept Elect & Electromagnetism Microelect Inst Seville IMSECNMCSIC Seville Spain

ISBN: (纸本)9781479900046

Lightweight security is currently a challenge in the field of cryptography. Most of applications designed for embedded scenarios often focus on authentication or on providing some form of anonymity and/or privacy. A well-known cryptographic element employed to provide such security is the HMAC construction. However, reported solutions are not suitable for constrained-resource scenarios due to their heavy approaches optimized for high-speed operations. In order to cover this lack, a lightweight implementation of HMAC based on the Photon family of hash functions is given in this work. Security of the construction against differential power attacks (DPA) is analyzed using a SASEBOII development board. Implementation and performance results for Xilinx Virtex-5 FPGAs of the HMAC structure is provided.

关键词： cryptography field programmable gate arrays file organisation message authentication

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AN EVENT-BASED MIDDLEWARE FOR THE REMOTE MANAGEMENT OF RUNTIME HArdWARE RECONFIGURATION

AN EVENT-BASED MIDDLEWARE FOR THE REMOTE MANAGEMENT OF RUNTI...

引用

23rd international conference on field programmable logic and applications (fpl)

作者： Philipp, Francois Glesner, Manfred Tech Univ Darmstadt Microelect Syst Res Grp D-64283 Darmstadt Germany

ISBN: (纸本)9781479900046

A procedure to remotely control hardware reconfiguration at runtime is introduced in this paper. Low-level interactions are abstracted by a middleware service that can be called by requests issued by the user or by the underlying operating system. The dynamic loading of hardware modules is managed by a kernel reacting to user-defined events with a customizable scheduling strategy. The system has been designed in a flexible and portable way to support most common runtime reconfiguration approaches and operating systems. Interactions with the middleware are based on commands allowing custom composition and scheduling of hardware modules after deployment. The operation of the middleware is illustrated with the example of a remotely reconfigurable sensor node in a high-performance wireless sensor network.

关键词： field programmable gate arrays logic design middleware scheduling

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CHARGE RECYCLING FOR POWER REDUCTION IN FPGA INTERCONNECT

CHARGE RECYCLING FOR POWER REDUCTION IN FPGA INTERCONNECT

引用

23rd international conference on field programmable logic and applications (fpl)

作者： Huda, Safeen Anderson, Jason Tamura, Hirotaka Univ Toronto Dept ECE Toronto ON Canada Fujitsu Labs Ltd Kawasaki Kanagawa Japan

ISBN: (纸本)9781479900046

We propose charge recycling (CR) to reduce power consumption in FPGAs. We take advantage of the property that many routing conductors are left unused in any FPGA implementation of an application. Charge recycling via the unused conductors reduces the amount of charge drawn from the supply, lowering energy consumption. We present a routing switch that operates in two modes: normal and CR, and describe the CAD tool changes needed to support CR at the routing and post-routing stages of the flow. Results show that dynamic power in the FPGA interconnect can be reduced by up to similar to 15-18.4% by the proposed techniques, depending on the performance constraints.

关键词： CAD field programmable gate arrays integrated circuit interconnections logic design power consumption

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MAGNITUDE MODULATION ON RECONFIGURABLE COMPUTING DEVICES

MAGNITUDE MODULATION ON RECONFIGURABLE COMPUTING DEVICES

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23rd international conference on field programmable logic and applications (fpl)

作者： Gomes, Marco Silva, Vitor Ferrao, Ricardo Univ Coimbra DEEC Polo 2 DEEC Inst Telecomunicacoes P-3030290 Coimbra Portugal

ISBN: (纸本)9781479900046

The control of the envelope's peak power by reducing overall peak-to-average power (PAPR) of transmitted RF signals can improve significantly the power efficiency of wireless communication systems both for single-carrier (SC) and multi-carrier (MC) transmissions. Multi-stage polyphase magnitude modulation (MPMM) has been recently proposed as an efficient PAPR reduction technique for SC signals. In this paper, we present a proof-of-concept prototype implementation in FPGA of the MPMM method. A prior study of the MPMM performance under fixed-point arithmetic is carried on, justifying decision criteria taken on MPMM's design targeted to FPGA.

关键词： field programmable gate arrays fixed point arithmetic logic design radiocommunication

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TILT: A MULTITHREADED VLIW SOFT PROCESSOR FAMILY

TILT: A MULTITHREADED VLIW SOFT PROCESSOR FAMILY

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23rd international conference on field programmable logic and applications (fpl)

作者： Ovtcharov, Kalin Tili, Ilian Steffan, J. Gregory Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 1A1 Canada

ISBN: (纸本)9781479900046

We propose TILT, an FPGA-based compute engine designed to highly-utilize multiple, varied, and deeply-pipelined functional units by leveraging thread-level parallelism and static compiler analysis and scheduling. For this work we focus on deeply-pipelined floating-point functional units of widely-varying latency, executing Hodgkin-Huxley neuron simulation as an example application, compiled with our LLVM-based scheduler. Targeting a Stratix IV FPGA, we explore architectural trade-offs by measuring area and throughput for designs with varying numbers of functional units, thread contexts, and memory banks.

关键词： field programmable gate arrays multi-threading multiprocessing systems parallelising compilers processor scheduling program diagnostics

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HIGH PERFORMANCE ARCHITECTURE FOR OBJECT DETECTION IN STREAMED VIDEOS

HIGH PERFORMANCE ARCHITECTURE FOR OBJECT DETECTION IN STREAM...

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23rd international conference on field programmable logic and applications (fpl)

作者： Zemcik, Pavel Juranek, Roman Musil, Petr Musil, Martin Hradis, Michal Brno Univ Technol Fac Informat Technol Dept Comp Graph & Multimedia CS-61090 Brno Czech Republic

ISBN: (纸本)9781479900046

In this paper, we introduce a novel architecture of an engine for high performance multi-scale detection of objects in videos based on WaldBoost training algorithm. The key properties of the architecture include processing of streamed data and low resource consumption. We implemented the engine in FPGA and we show that it can process 640 x 480 pixel video streams at over 160 fps without the need of external memory. We evaluate the design on the face detection task, compare it to state of the art designs, and discuss its features and limitations.

关键词： face recognition field programmable gate arrays object detection video streaming

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A PACKET CLASSIFIER USING LUT CASCADES BASED ON EVMDDS (K)

A PACKET CLASSIFIER USING LUT CASCADES BASED ON EVMDDS (K)

引用

23rd international conference on field programmable logic and applications (fpl)

作者： Nakahara, Hiroki Sasao, Tsutomu Matsuura, Munehiro Kagoshima Univ Kagoshima 890 Japan Meiji Univ Tokyo 101 Japan Kyushu Inst Technol Kitakyushu Fukuoka Japan

ISBN: (纸本)9781479900046

This paper presents a packet classifier using multiple LUT cascades based on edge-valued multi-valued decision diagrams (EVMDDs (k)). First, a set of rules for a packet classifier is partitioned into groups. Second, they are decomposed into field functions and Cartesian product functions. Third, they are represented by EVMDDs (k), and finally, they are converted to LUT cascades using adders. We implemented the proposed circuit on a Virtex 7 VC707 evaluation board. The system throughput is 345.60 Gbps for minimum packet size (40 Bytes). As for the normalized throughput (efficiency), the proposed one is 7.14 times better than existing FPGA implementations.

关键词： field programmable gate arrays pattern classification table lookup

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RAPID FPGA DESIGN PROTOTYPING THROUGH PRESERVATION OF SYSTEM logic: A CASE STUDY

RAPID FPGA DESIGN PROTOTYPING THROUGH PRESERVATION OF SYSTEM...

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23rd international conference on field programmable logic and applications (fpl)

作者： Haroldsen, Travis Nelson, Brent White, Brad Brigham Young Univ Dept Elect & Comp Engn NSF Ctr High Performance Reconfigurable Comp CHRE Provo UT 84602 USA

ISBN: (纸本)9781479900046

FPGA designs often contain significant amounts of logic such as a board support package that remains unaltered throughout the design process. However, during normal operation, standard FPGA implementation tools re-implement the entire system, including the unchanged logic, adding to the turn around time of design iterations. Recently, FPGA implementation flows have appeared that allow preserving parts of a previously implemented design. In this study, we evaluate the potential speedups in implementation time achievable through preserving the unchanging portion of a design's implementation. We perform these evaluations using Xilinx Partitions, Xilinx SmartGuide, and the HMFlow rapid implementation tool.

关键词： field programmable gate arrays logic design

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