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检索条件"任意字段=2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013"

共 228 条记录，以下是81-90 订阅

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ALTERING LUT CONFIGURATION FOR WEAR-OUT MITIGATION OF FPGA-MAPPED DESIGNS

ALTERING LUT CONFIGURATION FOR WEAR-OUT MITIGATION OF FPGA-M...

引用

23rd international conference on field programmable logic and applications (fpl)

作者： Rao, Parthasarathy M. B. Amouri, Abdulazim Kiamehr, Saman Tahoori, Mehdi B. Karlsruhe Inst Technol Inst Comp Engn D-76021 Karlsruhe Germany

ISBN: (纸本)9781479900046

Bias Temperature Instability (BTI) plays a significant role in transistor aging. As the device dimensions shrink due to technology scaling, this problem poses serious reliability issues. field programmable Gate Arrays (FPGAs) use very advanced nano-scaled CMOS technologies, which makes them vulnerable to BTI-induced aging. Previous studies have analyzed the relationship between the configuration of Look-Up Tables (LUTs) and the input signal probabilities against BTI-induced aging of LUTs. In this paper, we propose two methods to mitigate BTI-induced aging in LUTs. The mitigation is performed by manipulating the configuration of the used LUTs and their input signal probabilities, while maintaining the functionality of the mapped design. We implemented the proposed methods using the academic tool Verilog to Routing (VTR). The experimental results show that our methods can mitigate BTI-induced aging of LUT substantially and improve the lifetime of the FPGA-mapped designs, on average, by more than 200%.

关键词： CMOS integrated circuits ageing field programmable gate arrays integrated circuit reliability logic design table lookup

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FPGA BASED HArdWARE-SOFTWARE CO-DESIGNED DYNAMIC BINARY TRANSLATION SYSTEM

FPGA BASED HARDWARE-SOFTWARE CO-DESIGNED DYNAMIC BINARY TRAN...

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23rd international conference on field programmable logic and applications (fpl)

作者： Yao, Yuan Lu, Zhongyong Shi, Qingsong Chen, Wenzhi Zhejiang Univ Dept Comp Sci Hangzhou 310003 Zhejiang Peoples R China

ISBN: (纸本)9781479900046

Binary translation is used to allow applications of one instruction set architecture (ISA) to run on another, thereby maintaining the binary level compatibility across ISAs. Conventional software binary translation systems suffer performance loss because of architectural heterogeneity amongst ISAs, control flow translation and context switches. In this paper, we propose an FPGA based hardware-software co-designed dynamic binary translation (DBT) system, which moderates these issues at a low level of hardware cost. In our DBT system, we propose a MIPS condition code flags register and a modest ISA extension to bridge the architectural gap, a hardware address mapping mechanism to accelerate the handling of control flow instructions, and a scratchpad memory to reduce performance loss during context switches. We implement the system on Xilinx XC5VLX110T. Quantitative experiments reveal that the overall performance improvement is 56.1% over the baseline configuration, with only extra 1.4% of slices and 5.4% of BRAMs of Xilinx XC5VLX110T occupied.

关键词： field programmable gate arrays hardware-software codesign instruction sets program interpreters

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HIGH-LEVEL SYNTHESIS WITH BEHAVIORAL LEVEL MULTI-CYCLE PATH ANALYSIS

HIGH-LEVEL SYNTHESIS WITH BEHAVIORAL LEVEL MULTI-CYCLE PATH ...

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23rd international conference on field programmable logic and applications (fpl)

作者： Zheng, Hongbin Gurumani, Swathi T. Yang, Liwei Chen, Deming Rupnow, Kyle Adv Digital Sci Ctr Singapore Singapore Nanyang Technol Univ Singapore 639798 Singapore Univ Illinois Urbana IL USA

ISBN: (纸本)9781479900046

High-level synthesis (HLS) tools generate register transfer level (RTL) hardware descriptions through a process of resource allocation, scheduling and binding. Intuitively, RTL quality influences the logic synthesis quality. Specifically, the achievable clock rate, area, and latency in clock cycles will be determined by the RTL description. However, not all paths should receive equal logic synthesis effort -multi-cycle paths represent an opportunity to spend logic synthesis effort elsewhere to achieve better design quality. In this paper, we perform multi-cycle optimisation on chained functional operations. We couple HLS and logic synthesis synergistically so multi-cycle paths can be identified and optimised coherently across both behavioral and logic levels. In addition, we perform multi-cycle path analysis at the behavioral level efficiently. We prove that our technique examines all reachable circuit state and finds multi-cycle paths including control flow and guarding conditions that improve the flexibility and power of the technique. Compared to LegUp, we achieve average 55% execution time improvement, 29% area improvement, and 68% time-area product improvement targeting FPGA architecture.

关键词： field programmable gate arrays logic design

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PIPELINING COMPUTING STAGES IN CONFIGURABLE MULTICORE ARCHITECTURES

PIPELINING COMPUTING STAGES IN CONFIGURABLE MULTICORE ARCHIT...

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23rd international conference on field programmable logic and applications (fpl)

作者： Azarian, Ali Univ Porto Fac Engn P-4100 Oporto Portugal

ISBN: (纸本)9781479900046

Recently, there has been increasing interest on using tasklevel pipelining to accelerate the overall execution of applications mainly consisting of Producer-Consumer (P/C) tasks. In this PhD work we propose an approach to achieve pipelining execution of P/C pairs of tasks in FPGA-based multicore architectures. The current approach is able to speedup the overall execution of successive, data-dependent tasks, by using multiple cores and specific customization features provided by FPGAs. An important component of our approach is the use of customized inter-stage buffer schemes to communicate data and to synchronize the cores associated to the P/C tasks. To improve the performance, we propose a technique to optimize out-of-order communication between P/C pairs when the consumer requests more than once each data element produced, a behavior present in many applications (e.g., image processing). The current FPGA-based experimental results show the feasibility of our approach in both in-order and out-of-order P/C tasks. Moreover, the results using our approach to task-level pipelining and a multicore architecture reveal noticeable performance improvements for a number of benchmarks over a single core implementation without using task-level pipelining.

关键词： field programmable gate arrays pipeline processing

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DESIGN OF A MULTI GBPS SINGLE CARRIER DIGITAL BASEBAND FOR 60GHZ applications AND ITS FPGA IMPLEMENTATION

DESIGN OF A MULTI GBPS SINGLE CARRIER DIGITAL BASEBAND FOR 6...

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23rd international conference on field programmable logic and applications (fpl)

作者： Guntur, Surendra Jansen, Feike Hoogerbrugge, Jan Abkari, Lotfi Vos, Eric NXP Semicond Eindhoven Netherlands NXP Semicond Leuven Belgium

ISBN: (纸本)9781479900046

This paper describes the system architecture, design methodology and subsequent FPGA mapping of a millimeter wave digital baseband for wireless communication in the 60GHz spectral band. The baseband is designed to be compliant with the 802.11ad Single Carrier and Control PHY draft specifications and supports a data rate of 2.5Gbps at the physical layer. The demanding throughput and latency requirements are achieved with a parallel implementation. However, due to limited capacity of the FPGAs present in our prototype platform and complex partitioning requirements, only a scaled down version of the full single carrier baseband that operates at 1/10th the throughput of the specification could be mapped. A minimal real-time hardware MAC was also incorporated and coupled with a 60GHz RF beam-forming front-end to demonstrate file transfer between two independent FPGA prototyping systems. A system throughput of 59Mbps was achieved at the application layer using pi/2 QPSK modulation with a 13/16 LDPC code rate.

关键词： field programmable gate arrays parity check codes quadrature phase shift keying radiocommunication

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A FPGA DESIGN FOR HIGH SPEED FEATURE EXTRACTION FROM A COMPRESSED MEASUREMENT STREAM

A FPGA DESIGN FOR HIGH SPEED FEATURE EXTRACTION FROM A COMPR...

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23rd international conference on field programmable logic and applications (fpl)

作者： Richmond, Dustin Kastner, Ryan Irturk, Ali McGarry, John Univ Calif San Diego San Diego CA 92103 USA Congnex Corp San Diego CA USA

ISBN: (纸本)9781479900046

A common type of triangulation-based active 3D scanner outputs sets of surface coordinates, called profiles, by extracting the salient features of 2D images formed from an object illuminated by a narrow plane of light. Because a conventional 2D image must be digitized and processed for each profile, current systems do not always provide adequate speed and resolution to meet application demands. To address this challenge, a special purpose image sensor is being developed. Using Compressive Sensing, this sensor will be able to digitize compressed measurements of highly structured images, such as those formed in active 3D scanning, at a rate that would represent the conventional equivalent of 50G pixels/second. It is a significant challenge to process such a high-speed data stream at rates approaching real-time. Therefore, we present a single-chip FPGA design for the extraction of surface profiles from a compressed image stream originating from a 1024 by 768 pixel array at a rate of 14K images per second.

关键词： compressed sensing feature extraction field programmable gate arrays image coding image sensors logic design

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CRITICALITY-BASED ROUTING FOR FPGAS WITH REVERSE BODY BIAS SWITCH BOX ARCHITECTURES

CRITICALITY-BASED ROUTING FOR FPGAS WITH REVERSE BODY BIAS S...

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23rd international conference on field programmable logic and applications (fpl)

作者： Loke, Wei Ting Zhao, Wenfeng Ha, Yajun Xilinx Singapore 5 Changi Business Pk Vista Singapore 486040 Singapore Natl Univ Singapore Dept ECE Singapore 117576 Singapore

ISBN: (纸本)9781479900046

The use of reverse body bias (RBB) in circuit design is recognized to be a viable strategy for managing leakage power, a burning issue as process nodes continue to shrink beyond the 20nm realm. This technique is especially useful to FPGAs, which are able to tune RBB modes on-the-fly, offering leakage power reduction with very little impact to circuit speed. Most works today on RBB as applied to FPGAs are limited to the optimizations at the CLB level. We present a different architectural enhancement - the RBB switch box, and a routing algorithmdeploying net criticality ranking that exploits the flexibility of such an architecture. Compared to the non-RBB baseline, our scheme yields an average of 64.74% and 38.92% savings in the routing leakage power and the total power respectively (contributed solely by our routing architecture), with slight improvements to timing. The area overhead associated with our enhancement is also very small, with one unit area of biasing circuit 140x100 mu m(2) supporting similar to 340 switch boxes i.e. a 13x13 CLB array.

关键词： circuit optimisation field programmable gate arrays logic design network routing

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DEFECT-ROBUST FPGA ARCHITECTURES FOR INTELLECTUAL PROPERTY CORES IN SYSTEM LSI

DEFECT-ROBUST FPGA ARCHITECTURES FOR INTELLECTUAL PROPERTY C...

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23rd international conference on field programmable logic and applications (fpl)

作者： Amagasaki, Motoki Inoue, Kazuki Zhao, Qian Iida, Masahiro Kuga, Morihiro Sueyoshi, Toshinori Kumamoto Univ Grad Sch Sci & Technol Chuo Ku Kumamoto 8608555 Japan

ISBN: (纸本)9781479900046

In this paper, we propose fault-tolerant field-programmable gate array (FPGA) architectures and their computer-aid design (CAD) for intellectual property (IP) cores in system large-scale integration (LSI). Unlike discrete FPGAs, in which the integration scale can be made relatively large, programmable IP cores must correspond to arrays of various sizes. The key features of our architectures are regular tile structure, spare modules and bypass wires for fault avoidance, and configuration mechanism for single-cycle reconfiguration. In addition, we develop routing tools, namely EasyRouter for proposed architecture. This tool can handle various array sizes corresponding to developed programmable IP cores. In this evaluation, we compared the performances of conventional FPGA and the proposed fault-tolerant FPGA architectures. On average, our architectures have less than 2.2 times the area and 1.3 times the delay compared with conventional FPGA architectures. At the same time, conventional FPGAs cannot tolerate faults, whereas our architectures perform with a 90% success rate in fault avoidance for a ratio of faulty tiles of 1% or less.

关键词： fault tolerance field programmable gate arrays industrial property large scale integration logic CAD network routing

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FPGA BASED REKEYING FOR CRYPTOGRAPHIC KEY MANAGEMENT IN STORAGE AREA NETWORK

FPGA BASED REKEYING FOR CRYPTOGRAPHIC KEY MANAGEMENT IN STOR...

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23rd international conference on field programmable logic and applications (fpl)

作者： Wang, Yi Ha, Yajun Natl Univ Singapore Dept Elect & Comp Engn Singapore 117548 Singapore

ISBN: (纸本)9781479900046

Rekeying process plays an important role in secure large-scale Storage Area Network (SAN) applications. Software based Rekeying management could not completely prevent sensitive information leakage from theoretical and physical attacks. Traditional Rekeying process will suffer from decrypting the large data using the old key and encrypting it with the new key. In order to solve these problems, we proposed a FPGA based flexible and low-cost rekeying management to improve the security and reduce the processing time. In the proposed method, enveloping key is defined and added into the rekeying process to protect the real private key and the user's access key. During the rekeying process, the user's access key is substituted and send back to the user instead of real private key. In order to save the transformation time between the Policies Key Control (software) and key management (hardware), we proposed index extraction solution to shorten bit width of transformation from 256-bit to only 32-bit. Experimental results show that our proposed method only takes up 1.099 ms for rekeying process compared with the existing design with 3.91 ms execution time.

关键词： computer network management computer network security field programmable gate arrays private key cryptography public key cryptography storage area networks

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TITAN: ENABLING LARGE AND COMPLEX BENCHMARKS IN ACADEMIC CAD

TITAN: ENABLING LARGE AND COMPLEX BENCHMARKS IN ACADEMIC CAD

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23rd international conference on field programmable logic and applications (fpl)

作者： Murray, Kevin E. Whitty, Scott Liu, Suya Luu, Jason Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 1A1 Canada

ISBN: (纸本)9781479900046

Benchmarks play a key role in FPGA architecture and CAD research, enabling the quantitative comparison of tools and architectures. It is important that these benchmarks reflect modern designs which are large scale systems that make use of heterogeneous resources;however, most current FPGA benchmarks are both small and simple. In this paper we present Titan, a hybrid CAD flow that addresses these issues. The flow uses Altera's Quartus II FPGA CAD software to perform HDL synthesis and a conversion tool to translate the result into the academic BLIF format. Using this flow we created the Titan23 benchmark set, which consists of 23 large (90K-1.8M block) benchmark circuits covering a wide range of application domains. Using the Titan23 benchmarks and a detailed model of Altera's Stratix IV architecture we compared the performance and quality of VPR and Quartus II targeting the same architecture. We found that VPR is at least 2.7 x slower, uses 5.1 x more memory and 2.6 x more wire compared to Quartus II. Finally, we identified that VPR's focus on achieving a dense packing is responsible for a large portion of the wire length gap.

关键词： field programmable gate arrays logic CAD reconfigurable architectures

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