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检索条件"任意字段=2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013"

共 809 条记录，以下是91-100 订阅

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Vicilogic 2.0: Online Learning and Prototyping of Digital Systems Using PYNQ-Z1/-Z2 SoC 29

Vicilogic 2.0: Online Learning and Prototyping of Digital Sy...

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29th international symposium on Rapid System Prototyping, RSP 2018

作者： Morgan, Fearghal O'loughlin, Declan Audiger, Jeremy Boyer, Yohan Timlin-Canning, Niall Kepa, Krzysztof Cawley, Seamus Gallivan, Ian Bako, László Callaly, Frank National University of Ireland Galway Ireland Sapientia Hungarian University of Transylvania Romania

ISBN: (纸本)9781538675571

This paper presents viciLogic 2.0, a scalable, distributed online learning, hardware prototyping, client application and course creator platform for System on Chip (SoC)-based digital systems. User applications transparently link to a device in an array of Xilinx PYNQ-Zl or-Z2 SoC hardware in the cloud. The viciLogic prototype builder toolsuite (which integrates with the Xilinx Vivado industry-standard EDA tools) automates online (and local) SoC digital logic hardware prototyping, with integrated viciLogic user interface. The platform supports real-time user hardware input signal control and automated signal control, and probes the state of all user design internal and output signals. This enables the creation of responsive client applications and smart browser-based courses. Online course functions include guided lessons, SoC signal state monitoring for automatic course progression, knowledge checks, and user sandbox. The prototype builder uses source VHDL or Verilog projects created, simulated and synthesised in Vivado. The builder parses and modifies the HDL model to provide signal observability, integrates SoC resources (ARM, AXI interconnect, peripherals and viciLogic IP), and (using Vivado) generates the SoC hardware configuration bitstream and design metadata. The paper describes the viciLogic 2.0 server architecture, SoC prototype builder tool flow, client application creator, and online course creator. Two demonstration applications are presented, a counter course lesson step and a client application (16-bit single cycle computer, with IDE). © 2018 IEEE.

关键词： field programmable gate arrays (fpga)

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fpga Acceleration for Computational Glass-Free Displays 17

FPGA Acceleration for Computational Glass-Free Displays

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acm/sigda international symposium on field-programmable gate arrays

作者： He, Zhuolun Luo, Guojie Peking Univ Sch EECS Ctr Energy Efficient Comp & Applicat Beijing Peoples R China NUDT Collaborat Innovat Ctr High Performance Comp Changsha Hunan Peoples R China PKU UCLA Joint Res Inst Sci & Engn Beijing Peoples R China

ISBN: (纸本)9781450343541

The increasing computational power enables various new applications that are runtime prohibitive before. fpga is one of such computational power with both reconfigurability and energy efficiency. In this paper, we demonstrate the feasibility of eyeglasses-free displays through fpga acceleration. Specifically, we propose several techniques to accelerate the sparse matrix-vector multiplication and the L-BFGS iterative optimization algorithm with the consideration of the characteristics of fpgas. The experimental results show that we reach a 12.78X overall speedup of the glass-free display application.

关键词： fpga accelerator l-bfgs algorithm sparse matrix-vector multiplication light field display

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fpga 2013 - Proceedings of the 2013 acm/sigda international symposium on field programmable gate arrays

FPGA 2013 - Proceedings of the 2013 ACM/SIGDA International ...

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2013 acm/sigda international symposium on field programmable gate arrays, fpga 2013

ISBN: (纸本)9781450318877

The proceedings contain 29 papers. The topics discussed include: accelerating subsequence similarity search based on dynamic time warping distance with fpga;video-rate stereo matching using Markov random field TRW-S inference on a hybrid CPU+fpga computing platform;fully-functional fpga prototype with fine-grain programmable body biasing;sensing nanosecond-scale voltage attacks and natural transients in fpgas;word-length optimization beyond straight line code;word-length optimization beyond straight line code;embedding-based placement of processing element networks on fpgas for physical model simulation;a remote memory access infrastructure for global address space programming models in fpgas;architecture support for custom instructions with memory operations;high throughput and programmable online traffic classifier on fpga;and indirect connection aware attraction for fpga clustering.

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An OpenCL™ deep learning accelerator on Arria 10 17

An OpenCL™ deep learning accelerator on Arria 10

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2017 acm/sigda international symposium on field-programmable gate arrays, fpga 2017

作者： Aydonat, Utku O'Connell, Shane Capalija, Davor Ling, Andrew C. Chiu, Gordon R. Intel Corporation Toronto Canada

ISBN: (纸本)9781450343541

Convolutional neural nets (CNNs) have become a practical means to perform vision tasks, particularly in the area of image classification. fpgas are well known to be able to perform convolutions efficiently, however, most recent efforts to run CNNs on fpgas have shown limited advantages over other devices such as GPUs. Previous approaches on fpgas have often been memory bound due to the limited external memory bandwidth on the fpga device. We show a novel architecture written in OpenCL™, which we refer to as a Deep Learning Accelerator (DLA), that maximizes data reuse and minimizes external memory bandwidth. Furthermore, we show how we can use the Winograd transform to significantly boost the performance of the fpga. As a result, when running our DLA on Intel's Arria 10 device we can achieve a performance of 1020img/s, or 23img/s/W when running the AlexNet CNN benchmark. This comes to 1382 GFLOPs and is 10x faster with 8.4x more GFLOPS and 5.8x better efficiency than the state-of-the-art on fpgas. Additionally, 23 img/s/W is competitive against the best publicly known implementation of AlexNet on nVidia's TitanX GPU. © 2017 acm.

关键词： field programmable gate arrays (fpga)

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Accelerating Face Detection on programmable SoC Using C-Based Synthesis 17

Accelerating Face Detection on Programmable SoC Using C-Base...

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acm/sigda international symposium on field-programmable gate arrays

作者： Srivastava, Nitish Dai, Steve Manohar, Rajit Zhang, Zhiru Cornell Univ Sch Elect & Comp Engn Ithaca NY 14850 USA

ISBN: (纸本)9781450343541

High-level synthesis (HLS) enables designing at a higher level of abstraction to effectively cope with design complexity of emerging applications on modern programmable system-on-chip (SoC). While HLS continues to evolve with a growing set of algorithms, methodologies, and tools to efficiently map software designs onto optimized hardware architectures, there continues to lack realistic benchmark applications with sufficient complexity and enforceable constraints. In this paper we present a case study of accelerating face detection based on the Viola Jones algorithm on a programmable SoC using a C-based HLS flow. We also share our insights in porting a software-based design into a synthesizable implementation with HLS-specific data structures and optimizations. Our design is able to achieve a frame rate of 30 frames per second which is suitable for realtime applications. Our performance and quality of results are comparable to those of many traditional RTL implementations.

关键词： violajones fpga high level synthesis face detection SDSOC

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DATuner: An Extensible Distributed Autotuning Framework for fpga Design and Design Automation: (Abstract Only) 18

DATuner: An Extensible Distributed Autotuning Framework for ...

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Proceedings of the 2018 acm/sigda international symposium on field-programmable gate arrays

作者： Gai Liu Ecenur Ustun Shaojie Xiang Chang Xu Guojie Luo Zhiru Zhang Cornell University Ithaca NY USA IBM Research China Beijing China Peking University Beijing China

ISBN: (纸本)9781450356145

Mainstream fpga tools contain an extensive set of user-controlled compilation options and internal optimization strategies that significantly impact the design quality. These compilation and optimization parameters create a complex design space that human designers may not be able to effectively explore in a time-efficient manner. In this work we describe DATuner, an open-source extensible distributed autotuning framework for optimizing fpga designs and design automation tools using an ensemble of search techniques managed by multi-armed bandit algorithms. DATuner is designed for a distributed environment that uses parallel searches to amortize the significant runtime overhead of the CAD tools. DATuner provides convenient interface for extension to user-supplied tools, which enables the end users to apply DATuner to design tools/flows of their interest. We demonstrate the effectiveness and extensibility of DATuner using three case studies, which include clock frequency optimization for fpga compilation, fixed-point optimization, and autotuning logic synthesis transformations.

关键词： field-programmable gate array design automation distributed autotuning

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Accelerating Binarized Convolutional Neural Networks with Software-programmable fpgas 17

Accelerating Binarized Convolutional Neural Networks with So...

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acm/sigda international symposium on field-programmable gate arrays

作者： Zhao, Ritchie Song, Weinan Zhang, Wentao Xing, Tianwei Lin, Jeng-Hau Srivastava, Mani Gupta, Rajesh Zhang, Zhiru Cornell Univ Sch Elect & Comp Engn Ithaca NY 14853 USA Peking Univ Sch Elect Engn & Comp Sci Beijing Peoples R China Univ Calif Los Angeles Dept Elect Engn Los Angeles CA 90024 USA Univ Calif San Diego Dept Comp Sci & Engn La Jolla CA 92093 USA

ISBN: (纸本)9781450343541

Convolutional neural networks (CNN) are the current state-of-the-art for many computer vision tasks. CNNs outperform older methods in accuracy, but require vast amounts of computation and memory. As a result, existing CNN applications are typically run on clusters of CPUs or GPUs. Research on fpga acceleration of CNN workloads has achieved reductions in power and energy consumption. However, large GPUs outperform modern fpgas in throughput, and the existence of compatible deep learning frameworks give GPUs a significant advantage in programmability. Recent work in machine learning demonstrates the potential of very low precision CNNs - i.e., CNNs with binarized weights and activations. Such binarized neural networks (BNNs) appear well suited for fpga implementation, as their dominant computations are bitwise logic operations and their memory requirements are greatly reduced. A combination of low-precision networks and high-level design methodology may help address the performance and productivity gap between fpgas and GPUs. In this paper, we present the design of a BNN accelerator that is synthesized from C++ to fpga-targeted Verilog. The accelerator outperforms existing fpga-based CNN accelerators in GOPS as well as energy and resource efficiency.

关键词： binarized convolutional networks deep learning high-level synthesis reconfigurable computing fpgas binarized

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An Energy-Efficient Design-Time Scheduler for fpgas Leveraging Dynamic Frequency Scaling Emulation 17

An Energy-Efficient Design-Time Scheduler for FPGAs Leveragi...

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acm/sigda international symposium on field-programmable gate arrays

作者： Loke, Wei Ting Koay, Chin Yang Natl Univ Singapore Singapore Singapore Xilinx San Jose CA USA

ISBN: (纸本)9781450343541

We present a design-time tool, EASTA, that combines the feature of reconfigurability in fpgas and Dynamic Frequency Scaling to realize an efficient multiprocessing scheduler on a single-fpga system. Multiple deadlines, reconvergent nodes, flow dependency and processor constraints of the multiprocessor problem on general task graphs are rigorously taken into consideration. EASTA is able to determine the minimum number of processing elements required to create a feasible schedule and dynamically adjust the clock speed of each processing element to reclaim slack. The schedule is represented by an efficient tree-based lookup table. We evaluate the EASTA tool using randomly generated task graphs and demonstrate that our framework is able to produce energy savings of 39.41% and 33% for task graphs of size 9.

关键词： field programmable gate Array Low Power Dynamic Frequency Scaling Design-Time Scheduling

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Can fpgas Beat GPUs in Accelerating Next-Generation Deep Neural Networks? 17

Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neu...

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acm/sigda international symposium on field-programmable gate arrays

作者： Nurvitadhi, Eriko Venkatesh, Ganesh Sim, Jaewoong Marr, Debbie Huang, Randy Ong, Jason Gee Hock Liew, Yeong Tat Srivatsan, Krishnan Moss, Duncan Subhaschandra, Suchit Boudoukh, Guy Intel Corp Accelerator Architecture Lab Santa Clara CA 95051 USA Intel Corp Programmable Solut Grp Santa Clara CA 95051 USA Intel Corp FPGA Prod Team Santa Clara CA 95051 USA Intel Corp Comp Vis Grp Santa Clara CA 95051 USA

ISBN: (纸本)9781450343541

Current-generation Deep Neural Networks (DNNs), such as AlexNet and VGG, rely heavily on dense floating-point matrix multiplication (GEMM), which maps well to GPUs (regular parallelism, high TFLOP/s). Because of this, GPUs are widely used for accelerating DNNs. Current fpgas offer superior energy efficiency (Ops/Watt), but they do not offer the performance of today's GPUs on DNNs. In this paper, we look at upcoming fpga technology advances, the rapid pace of innovation in DNN algorithms, and consider whether future high-performance fpgas will outperform GPUs for next-generation DNNs. The upcoming Intel (R) 14-nm Stratix (TM) 10 fpgas will have thousands of hard floating-point units (DSPs) and on-chip RAMs (M20K memory blocks). They will also have high bandwidth memories (HBMs) and improved frequency (HyperFlex (TM) core architecture). This combination of features brings fpga raw floating point performance within striking distance of GPUs. Meanwhile, DNNs are quickly evolving. For example, recent innovations that exploit sparsity (e.g., pruning) and compact data types (e.g., 1-2 bit) result in major leaps in algorithmic efficiency. However, these innovations introduce irregular parallelism on custom data types, which are difficult for GPUs to handle but would be a great fit for fpga's extreme customizability. This paper evaluates a selection of emerging DNN algorithms on two generations of Intel fpgas (Arria (TM) 10, Stratix (TM) 10) against the latest highest performance Titan X Pascal GPU. We created a customizable DNN accelerator template for fpgas and used it in our evaluations. First, we study various GEMM operations for next-generation DNNs. Our results show that Stratix 10 fpga is 10%, 50%, and 5.4x better in performance (TOP/sec) than Titan X Pascal GPU on GEMM operations for pruned, Int6, and binarized DNNs, respectively. Then, we present a detailed case study on accelerating Ternary ResNet which relies on sparse GEMM on 2-bit weights (i.e., weights constrai

关键词： Deep Learning Accelerator Intel Stratix 10 fpga GPU

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Learning Convolutional Neural Networks for Data-Flow Graph Mapping on Spatial programmable Architectures 17

Learning Convolutional Neural Networks for Data-Flow Graph M...

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acm/sigda international symposium on field-programmable gate arrays

作者： Yin, Shouyi Liu, Dajiang Sun, Lifeng Lin, Xinhan Liu, Leibo Wei, Shaojun Tsinghua Univ Beijing Peoples R China

ISBN: (纸本)9781450343541

Data flow graph (DFG) mapping is critical for the compiling of spatial programmable architecture, where compilation time is a key factor for both time-to-market requirement and mapping successful rate. Inspired from the great progress made in tree search game using deep neural network, we proposed a framework for learning convolutional neural networks for mapping DFGs onto spatial programmable architectures. Considering that mapping is a process from source to target, we present a dual-input neural network capturing features from both DFGs in applications and Process Element Array (PEA) in spatial programmable architectures. In order to train the neural network, algorithms are designed to automatically generate a data set from PEA intermediate states of preprocessed DFG. Finally, we demonstrate that the trained neural network can get high identifying accuracy of mapping quality and our proposed mapping approach are competitive with state-of-the-art DFG mapping algorithms in performance while the compilation time is greatly reduced.

关键词： DFG reconfigurable architecture mapping convolutional neural network

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