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检索条件"任意字段=2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013"

共 809 条记录，以下是101-110 订阅

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fpga 2014 - Proceedings of the 2014 acm/sigda international symposium on field programmable gate arrays

FPGA 2014 - Proceedings of the 2014 ACM/SIGDA International ...

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2014 acm/sigda international symposium on field programmable gate arrays, fpga 2014

ISBN: (纸本)9781450326711

The proceedings contain 30 papers. The topics discussed include: fast and effective placement and routing directed high-level synthesis for fpgas;optimizing effective interconnect capacitance for fpga power reduction;towards interconnect-adaptive packing for fpgas;modular multi-ported SRAM-based memories;scalable multi-access flash store for big data analytics;cad and routing architecture for interposer-based multi-fpga systems;memory block based scan-BIST architecture for application-dependent fpga testing;fpga-based biophysically-meaningful modeling of olivocerebellar neurons;square-rich fixed point polynomial evaluation on fpgaS;a power side-channel-based digital to analog converter for Xilinx fpgas;MORP: MakeSpan optimization for processors with an embedded reconfigurable fabric;a scalable sparse matrix-vector multiplication kernel for energy-efficient sparse-BLAs on fpgas;and Wordwidth, instructions, looping, and virtualization: the role of sharing in absolute energy minimization.

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A Low-power APUF-based Environmental Abnormality Detection Framework 22

A Low-power APUF-based Environmental Abnormality Detection F...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Gu, Hongxiang Xu, Teng Potkonjak, Miodrag Univ Calif Los Angeles Comp Sci Dept Los Angeles CA 90095 USA

ISBN: (纸本)9781509060238

Physical unclonable functions (PUFs) take advantage of the effect of process variation on hardware to obtain their unclonability. Traditional PUF design only focuses on the analog signals of circuits. An arbiter PUF, for example, generates responses by racing delay signals. Implementations of such PUFs usually employ large area and power consumption while providing very low throughput. To address this problem, we propose an energy efficient PUF design in such a way that it races analog signals and computes digital logic simultaneously. More importantly, the analog portion of the circuit (racing) shares a large amount of hardware resources with the digital portion of the circuit (computing) by introducing only small overhead in terms of area and power. Our test results on Spartan-6 field-programmable gate array (fpga) platforms indicate that by combining the two outputs, our design enables much larger PUF output throughput, better randomness and less power consumption compared to traditional PUFs.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Measuring the Power-Constrained Performance and Energy Gap between fpgas and Processors 17

Measuring the Power-Constrained Performance and Energy Gap b...

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acm/sigda international symposium on field-programmable gate arrays

作者： Ye, Andy Gean Ganesan, Karthik Ryerson Univ Toronto ON Canada Univ Toronto Toronto ON Canada

ISBN: (纸本)9781450343541

This work measures the performance and power consumption gap between the current generation of low power fpgas and low power microprocessors (microcontrollers) through an implementation of the Canny edge detection algorithm. In particular, the algorithm is implemented on Altera MAX 10 fpgas and its performance and power consumption are then compared to the same algorithm implemented on the STMicroelectronics' implementation of the ARM M-series microcontrollers. We found an extremely high, four- to five-orders of magnitude, performance advantage of the fpgas over the microcontrollers, which is much greater than any previously reported values in fpgas vs. processors studies. Furthermore, this speedup only comes at a cost of 1.2x to 15x higher power consumption, which gives fpgas a significant advantage in energy efficiency. We also observe, however, the current generation of low power fpgas have significantly higher static power consumption than the microcontrollers. In particular, the low power fpgas consume more static power than the total power consumption of the lowest power consuming microcontrollers, rendering the fpgas inoperable under the power budgets of these processors. Furthermore, this high static power consumption exists despite the fact that the fpgas are implemented on a low leakage 55nm process with dual supply voltages while the microcontrollers are implemented on a conventional, single supply voltage, 90nm process. Consequently, our results indicate that it is particular important for future research to address the static power consumption of low power fpgas while maintaining logic capacity so the performance and energy efficiency advantages of the fpgas can be fully utilized in the extremely low power application domain that are driven by batteries with very small form factors and emerging small scale energy harvesting technologies.

关键词： field programmable gate arrays (fpgas) Low-Power fpgas fpga vs. Microcontroller Performance Energy Efficiency

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ASAP: Accelerated Short Read Alignment on programmable Hardware 17

ASAP: Accelerated Short Read Alignment on Programmable Hardw...

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acm/sigda international symposium on field-programmable gate arrays

作者： Banerjee, Subho S. el-Hadedy, Mohamed Lim, Jong B. Chen, Daniel Kalbarczyk, Zbigniew T. Chen, Deming Iyer, Ravishankar K. Univ Illinois Champaign IL USA

ISBN: (纸本)9781450343541

The proliferation of high-throughput sequencing machines allows for the rapid generation of billions of short nucleotide fragments in a short period. This massive amount of sequence data can quickly overwhelm today's storage and compute infrastructure. This poster explores the use of hardware acceleration to significantly improve the runtime of short-read alignment (SRA), a crucial step in pre-processing sequenced genomes. It presents the design and implementation of ASAP, an accelerator for computing Levenshtein distance (LD) in the context of the SRA problem. LD computation is a prominent underlying mathematical kernel that is common to a large number of SRA tools (e.g., BLAST, BWA, SNAP) and is responsible for 50-70% of their runtime. These algorithms mentioned above calculate the exact value of LD between nucleotide strings but only use them to build a total ordering (an ordered list) of the most likely point of origin in the genome. ASAP computes an approximation of LD by encoding computation in propagation delay of circuit elements. This approximation is calculated in an accelerated fashion in hardware and preserves the original total ordering of LDs produced by the traditional algorithms. This computation is performed by constructing circuits that comprise the recursive definition of the LD computation and measuring propagation delay of a signal entering and leaving the circuit. Additionally, ASAP can explore large portions of the search space (substrings of the strings being compared) within one clock cycle, and ignore parts of the search space that does not contribute to an answer. Our design is implemented on an Altera Stratix V fpga in an IBM POWER8 system using the CAPI interface for cache coherence across the CPU and fpga. Our design is 200x faster (median measurement) than the equivalent C implementation of the kernel running on the host processor and 2.2x faster for an end-to-end alignment tool for 120-150bp short-read sequences.

关键词： fpga Bioinformatics Genomics

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Bit-width Based Resource Partitioning for CNN Acceleration on fpga 25

Bit-width Based Resource Partitioning for CNN Acceleration o...

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25th IEEE Annual international symposium on field-programmable Custom Computing Machines (FCCM)

作者： Guo, Jianxin Yin, Shouyi Ouyang, Peng Liu, Leibo Wei, Shaojun Tsinghua Univ Inst Microelect Beijing Peoples R China

ISBN: (纸本)9781538640371

Convolutional neural networks (CNNs) have achieved great success in many applications. Recently, various fpga-based accelerators have been proposed to improve the performance of CNNs. However, current most fpga-based methods use single bit-width selection for all CNN layers, which lead to very low resource utilization efficiency and difficulty in further performance improvement. In this paper, we propose a new approach utilizing bit-width partitioning of fpga DSP resources to improve the performance and resource utilization efficiency of CNN accelerator. Moreover, we use optimization approach to find the optimal allocation plan for DSP resources. On a Xilinx Virtex-7 fpga, our design approach achieves performance over the state-of-the-art fpga-based CNN accelerators from 5.48x to 7.25x and by 6.21x on average, when we evaluate the popular CNNs.

关键词： field programmable gate arrays (fpga)

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Prototyping dynamic task migration on heterogeneous reconfigurable systems 28

Prototyping dynamic task migration on heterogeneous reconfig...

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2017 28th international symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, RSP 2017

作者： Wicaksana, Arief Bourge, Alban Muller, Olivier Sasongko, Arif Rousseau, Frédéric Univ. Grenoble Alpes TIMA CNRS Grenoble France Institut Teknologi Bandung Bandung Indonesia

ISBN: (纸本)9781450354189

Reconfigurable devices, such as fpgas, have been known to offer an excellent performance and a high efficiency in computation. Due to their improving capacity and more efficient architecture recently, there are growing interests in using fpgas as coprocessors in reconfigurable systems. However, fpgas still lack the support in dynamic scheduling, e.g. to manage multiple tasks or users in a system. Performing runtime task relocation or load distribution is not possible unless the reconfigurable system supports dynamic task migration. Such ability requires the automation of configuration and context management in reconfigurable architecture, which is not available in the existing solutions. In this paper, we propose a framework for prototyping dynamic task migration between heterogeneous fpgas. A task running on one fpga can be suspended and resumed on another fpga with different architecture. The extraction and restoration of fpga registers and memory values are possible due to the task-specific extraction mechanism provided by the tasks. The proposed framework exploits a high-performance embedded processor tightly-coupled to an fpga to automatically manage the configuration and context. It utilizes two popular heterogeneous reconfigurable systems in the implementation, Xilinx Zynq ZC706 and Altera Arria V SoC. Tests are performed using graphical and non-graphical benchmark applications and performance results are presented. © 2017 acm.

关键词： field programmable gate arrays (fpga)

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Exploring Sparsity of Firing Activities and Clock Gating for Energy-Efficient Recurrent Spiking Neural Processors 22

Exploring Sparsity of Firing Activities and Clock Gating for...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Liu, Yu Jin, Yingyezhe Li, Peng Texas A&M Univ Dept Elect & Comp Engn College Stn TX 77843 USA

ISBN: (纸本)9781509060238

As a model of recurrent spiking neural networks, the Liquid State Machine (LSM) offers a powerful brain-inspired computing platform for pattern recognition and machine learning applications. While operated by processing neural spiking activities, the LSM naturally lends itself to an efficient hardware implementation via exploration of typical sparse firing patterns emerged from the recurrent neural network and smart processing of computational tasks that are orchestrated by different firing events at runtime. We explore these opportunities by presenting a LSM processor architecture with integrated on-chip learning and its fpga implementation. Our LSM processor leverage the sparsity of firing activities to allow for efficient event-driven processing and activity-dependent clock gating. Using the spoken English letters adopted from the TI46 [1] speech recognition corpus as a benchmark, we show that the proposed fpga-based neural processor system is up to 2 9 % more energy efficient than a baseline LSM processor with little extra hardware overhead.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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fpga-based Strong PUF with Increased Uniqueness and Entropy Properties 50

FPGA-based Strong PUF with Increased Uniqueness and Entropy ...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： Gu, Chongyan Hanley, Neil O'Neill, Maire Queens Univ Belfast CSIT ECIT Belfast BT3 9DT Antrim North Ireland

ISBN: (纸本)9781467368537

Physical unclonable functions (PUFs), are a type of physical security primitive which enable identification and authentication of hardware devices, such as field programmable gate arrays (fpgas) and application specific integrated circuits (ASICs). Arbiter PUFs were the first proposed Strong PUF and are also widely studied. However, these designs often sutTer from poor uniqueness and reliability characteristics leaving them vulnerable to modeling attacks, as well as being difficult to implement on fpgas due to the physical layout restrictions. Some more recent designs based around non-linear voltage transfer characteristics, or non-linear currents improve the resistance against modeling attacks. However they can only be implemented on ASICs due to their voltage/current requirements. To address this problem, we propose a new PUF circuit that otTers a significantly higher theoretical entropy than the traditional Arbiter PUF construction, and which is specifically designed for fpgas. The proposed work is verified on a low-cost Nexys4 board which contains a XiIinx Artix-7 fpga fabricated at 28nm. The experimental results give a uniqueness of 20 %, considerably higher than the reported 9 % of a traditional Arbiter PUF design, and an expected reliability of similar to 96 % over an environmental temperature range of 0 degrees C to 75 degrees C, with a reliability of approximate to 92 % with +/- 10 % variation in supply voltage.

关键词： Delays field programmable gate arrays Entropy Reliability engineering Security Integrated circuit modeling

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Simulation-based circuit-activity estimation for fpgas containing hard blocks 28

Simulation-based circuit-activity estimation for FPGAs conta...

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2017 28th international symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, RSP 2017

作者： Seeley, Sean Sankaranaryanan, Vidya Deveau, Zack Patros, Panagiotis Kent, Kenneth B. Faculty of Computer Science University of New Brunswick Canada

ISBN: (纸本)9781450354189

fpgas are electronic devices that are programmable and can functionally perform equivalently to a number of other circuits. fpgas are used for both rapid and cheap prototyping of new circuit designs as well as for replacing outdated chip models. Due to their complexity, circuits cannot be practically designed by hand;instead, specialized Computer Aided Design (CAD) software performs this complex task. A major concern for devices is power requirements, which can have adverse effects on both the environment and users. The power requirements of a circuit can be directly connected with its activity, which can be estimated by the CAD tools. In this work, we focus on the open source Verilog-To-Routing (VTR) CAD software and propose an improved activity estimation tool using VTR's synthesizer (Odin II) that extends beyond the capabilities of its current estimator (ACE2), such as proper black box activity propagation and support for circuits containing no clocks or more than one clock. Our results are experimentally evaluated with VTR's fpga architectures and benchmark circuits. © 2017 acm.

关键词： field programmable gate arrays (fpga)

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Approximate Memory Compression for Energy-efficiency 22

Approximate Memory Compression for Energy-efficiency

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Ranjan, Ashish Raha, Arnab Raghunathan, Vijay Raghunathan, Anand Purdue Univ Sch Elect & Comp Engn W Lafayette IN 47907 USA

ISBN: (纸本)9781509060238

Memory subsystems are a major energy bottleneck in computing platforms due to frequent transfers between processors and off-chip memory. We propose approximate memory compression, a technique that leverages the intrinsic resilience of emerging workloads such as machine learning and data analytics to reduce off-chip memory traffic and energy. To realize approximate memory compression, we enhance the memory controller to be aware of memory regions that contain approximation-resilient data, and to transparently compress/decompress the data written to/read from these regions. To provide control over approximations, the quality-aware memory controller conforms to a specified error constraint for each approximate memory region. We design a software interface that programmers can use to identify data structures that are resilient to approximations. We also propose a runtime quality control framework that automatically determines the error constraints for the identified data structures such that a given target application-level quality is maintained. We evaluate our proposal by implementing a hardware prototype using the Intel UniPHY-DDR3 memory controller and NIOS-II processor, a Hynix DDR3 DRAM module, and a Stratix-IV fpga development board. Across a suite of 8 machine learning benchmarks, approximate memory compression obtains a 1.28 x benefit in DRAM energy and a simultaneous 11.5% improvement in execution time for a small (< 1.5%) loss in output quality.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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