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检索条件"任意字段=2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013"

共 809 条记录，以下是111-120 订阅

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OLAF′16: Second international Workshop on Overlay Architectures for fpgas 16

OLAF′16: Second International Workshop on Overlay Architect...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： So, Hayden Kwok-Hay Wawrzynek, John Univ Hong Kong Dept Elect & Elect Engn Hong Kong Hong Kong Peoples R China Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA

ISBN: (纸本)9781450338561

The Second international Workshop on Overlay Architectures for fpgas is held in Monterey, California, USA, on February 21, 2016 and co-located with fpga 2016: The 24th acm/sigda international symposium on field programmable gate arrays. The main objective of the workshop is to address how overlay architectures can help address the challenges and opportunities provided by fpga-based reconfigurable computing. The workshop provides a venue for researchers to present and discuss the latest developments in fpga overlay architecture and related areas. We have assembled a program of six refereed papers and a panel discussion with prominent experts in the field.

关键词： fpga Overlay architecture

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Towards PVT-Tolerant Glitch-Free Operation in fpgas 16

Towards PVT-Tolerant Glitch-Free Operation in FPGAs

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Huda, Safeen Anderson, Jason Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9781450338561

Glitches are unnecessary transitions on logic signals that needlessly consume dynamic power. Glitches arise from imbalances in the combinational path delays to a signal, which may cause the signal to toggle multiple times in a given clock cycle before settling to its final value. In this paper, we propose a low-cost circuit structure that is able to eliminate a majority of glitches. The structure, which is incorporated into the output buffers of fpga logic elements, suppresses pulses on buffer outputs whose duration is shorter than a configurable time window (set at the time of fpga configuration). Glitches are thereby eliminated "at the source" ensuring they do not propagate into the high-capacitance fpga interconnect, saving power. An experimental study, using Altera commercial tools for power analysis, demonstrates that the proposed technique reduces 70% of glitches, at a cost of 1% reduction in speed performance.

关键词： field programmable gate arrays (fpga)

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Pico-TDC: a novel fpga-based TDC with 2.2ps RMS timing resolution

Pico-TDC: a novel FPGA-based TDC with 2.2ps RMS timing resol...

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IEEE Nuclear Science symposium and Medical Imaging Conference (NSS/MIC) / 24th international symposium on Room-Temperature Semiconductor X-Ray and Gamma-Ray Detectors

作者： Sui, T. Zhao, Z. Xie, S. Huang, Q. Xu, J. Peng, Q. Huazhong Univ Sci & Technol Wuhan Hubei Peoples R China Shanghai Jiao Tong Univ Shanghai Peoples R China Lawrence Berkeley Natl Lab Dept Mol Biophys & Integrated Bioimaging Berkeley CA 94720 USA

ISBN: (纸本)9781538622827

The purpose of this work is to develop low-cost high-performance TDCs to meet the requirement from the next generation sub-lOps TOF-PET catnera. A TOF-PET system may need hundreds of high resolution TDCs to read timing from many detectors. fpga-based TDC designs, such as conventional delay-line (DL) TDCs and Wave-Unions (WU) TDCs, are a more viable solutions compared with expensive ASIC-based TDCs. However, the performances of those fpga-based TDCs are more or less depended on the specific structures and performances of the delay lines, which are usually the carry chains in the adders of a fpga. In this paper, we present a new method called Pico-TDC method to construct the TDCs in fpga. The uniqueness of the Pico-TDC method is to use single registers in the fpga as low-precision TDCs, and to combine many of those low-precision TDCs to construct a high-precision TDC. The advantages of Pico-TDC method are: (1) the timing performance of a Pico-TDC is not limited by the performance of delay lines in the fpga. As a result, it is possible to achieve unprecedented resolution with a low-cost fpga. (2) Hundreds of high-performance Pico-TDCs can he constructed in a low-cost fpga which normally has millions of registers. (3) Theoretically, the Pico-TDCs can be conveniently migrated from one fpga to another, regardless of the differences in the internal structures of the fpgas. We have successfully constructed four channels of Pico-TDCs in a low-cost fpga (Altera Cyclone V SCEBA4F23C7N, price: $66.63). Each TDC uses 640 registers (low-precision TDCs). The four Pico-TDCs were tested with both the internal and the external pulses. The RMS of the timing measurements is 2.2 ps. The temperature stability is excellent. We conclude that Pico-TDCs have excellent timing performance which meets the requirement of the next generation sub-lOps TOF-PET.

关键词： field programmable gate arrays Timing Registers Temperature measurement Clocks Quantization (signal) Next generation networking

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GPU-Accelerated High-Level Synthesis for Bitwidth Optimization of fpga Datapaths 16

GPU-Accelerated High-Level Synthesis for Bitwidth Optimizati...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Kapre, Nachiket Ye, Deheng Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore

ISBN: (纸本)9781450338561

Bitwidth optimization of fpga datapaths can save hardware resources by choosing the fewest number of bits required for each datapath variable to achieve a desired quality of result. However, it is an NP-hard problem that requires unacceptably long runtimes when using sequential CPU-based heuristics. We show how to parallelize the key steps of bitwidth optimization on the GPU by performing a fast brute-force search over a carefully constrained search space. We develop a high-level synthesis methodology suitable for rapid prototyping of bitwidth-annotated RTL code generation using gcc's GIMPLE backend. For range analysis, we perform parallel evaluation of sub-intervals to provide tighter bounds compared to ordinary interval arithmetic. For bitwidth allocation, we enumerate the different bitwidth combinations in parallel by assigning each combination to a GPU thread. We demonstrate up to 10-1000x speedups for range analysis and 50-200x speedups for bitwidth allocation when comparing NVIDIA K20 GPU implementation to an Intel Core i5-4570 CPU while maintaining identical solution quality across various benchmarks. This allows us to generate tailor-made RTL with minimum bitwidths in hundreds of milliseconds instead of hundreds of minutes when starting from high-level C descriptions of dataflow computations.

关键词： field programmable gate arrays (fpga)

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FCUDA-SoC: Platform Integration for field-programmable SoC with the CUDA-to-fpga Compiler 16

FCUDA-SoC: Platform Integration for Field-Programmable SoC w...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Nguyen, Tan Gurumani, Swathi Rupnow, Kyle Chen, Deming Adv Digital Sci Ctr Singapore Singapore Univ Illinois Elect & Comp Engn Urbana IL 61801 USA

ISBN: (纸本)9781450338561

Throughput oriented high level synthesis allows efficient design and optimization using parallel input languages. Parallel languages offer the benefit of parallelism extraction at multiple levels of granularity, offering effective design space exploration to select efficient single core implementations, and easy scaling of parallelism through multiple core instantiations. However, study of high level synthesis for parallel languages has concentrated on optimization of core and on-chip communications, while neglecting platform integration, which can have a significant impact on achieved performance. In this paper, we create an automated flow to perform efficient platform integration for an existing CUDAto-RTL throughput oriented HLS, and we open source the FCUDA tool, platform integration, and benchmark applications. We demonstrate platform integration of 16 benchmarks on two Zynq-based systems in bare-metal and OS mode. We study implementation optimization for platform integration, compare to an embedded GPU (Tegra TK1) and verify designs on a Zedboard Zynq 7020 (bare-metal) and Omnitek Zynq 7045 (OS).

关键词： System-on-chip

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A prototype MR insert PET detector with strip-line readout

A prototype MR insert PET detector with strip-line readout

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IEEE Nuclear Science symposium and Medical Imaging Conference (NSS/MIC) / 24th international symposium on Room-Temperature Semiconductor X-Ray and Gamma-Ray Detectors

作者： Kim, Heejong Hua, Yuexuan Xi, Daoming Xie, Qingguo Eclov, Neville Chen, Hsing-Tsuen Chen, Chin-Tu Chou, Cheng-Ying Kao, Chien-Min Univ Chicago Dept Radiol Chicago IL 60637 USA Huazhong Univ Sci & Technol Dept Biomed Engn Wuhan Hubei Peoples R China Natl Taiwan Univ Dept Bioind Mechatron Engn Taipei Taiwan

ISBN: (纸本)9781538622827

We are developing a MR insert PET detector using SiPM for small animal imaging. Our detector design is based on the strip-line signal readout that we have developed to efficiently handle large amount signals for SiPM-based TOF PET. The strip line readout has an advantageous feature suitable for building PET integrated within MR. In strip-line readout, the signal digitization is accomplished remotely from the detection module, thereby the front-end electronics of the detector within MR is minimal;the interference between two systems, e.g., magnetic field distortion due to PET, can be minimized accordingly. The feasibility of the strip-line readout for PET/MR has been demonstrated in our previous study. The current prototype MR insert PET is comprised of 8 detector modules, which are installed in a plastic cylindrical supporting structure. Each detector module consists of 8x4 LYSO arrays (3x3x10 mm(3) each) and two Hamamatsu S13361-3050NE-04 MPPC arrays (4x4, 3.2 mm pitch);32 SiPM signals are routed in 4 strip-lines so that 8 LYSO/SiPM signals in a row are connected to each strip-line. The signals from strip-lines are fed to a 72-ch multi-voltage threshold (MVT) digitizer, which digitizes the input by TDCs implemented in fpga. Experiments have been carried out to evaluate the detector performance, and image reconstruction also has been performed for a simple shape object. In the paper, the detail on the development of the MR insert PET are explained, and preliminary test results are presented.

关键词： Detectors Image reconstruction Time measurement Prototypes Animals field programmable gate arrays Shape

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Dissecting Xeon + fpga: Why the integration of CPUs and fpgas makes a power difference for the datacenter: Invited Paper 16

Dissecting Xeon + FPGA: Why the integration of CPUs and FPGA...

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21st IEEE/acm international symposium on Low Power Electronics and Design, ISLPED 2016

作者： Schmit, Herman Huang, Randy Intel Corporation San JoseCA United States

ISBN: (纸本)9781450341851

Intel's Xeon roadmap includes package-integrated fpgas in every new generation. In this talk, we will dissect why this is such a powerful combination at this time of great change in datacenter workloads. We will show how power savings within the CPU complex is a significant multiplier for power savings in the datacenter as a whole. Focusing on the domain of machine learning, we will present the recent evolution of data types and operators, and make the case that fpgas are the path to facilitate this continued evolution. Finally, we will discuss the criticality of the close coupling of the CPU and the fpga. This coupling facilitates high bandwidth and low latency communication that is required for the development, debugging and deployment of heterogeneous applications. © 2016 Authors.

关键词： field programmable gate arrays (fpga)

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Inter-fpga Routing Environment for Performance Exploration of Multi-fpga Systems 27

Inter-FPGA Routing Environment for Performance Exploration o...

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27th international symposium on Rapid System Prototyping (RSP) - Shortening the Path from Specification to Prototype

作者： Farooq, Umer Chotin-Avot, Roselyne Azeem, Moazam Ravoson, Maminionja Turki, Mariem Mehrez, Habib UPMC Univ Paris 06 Sorbonne Univ CNRS LIP6 Paris France

ISBN: (纸本)9781450345354

Multi-fpga platforms are a popular choice today for complex system prototyping because they offer high execution speed, low cost, and real world testing experience. However, performance of multi-fpga based systems is severely affected by widening logic to I/O gap in fpgas. In order to address the performance issue, in this work, we propose an exploration and optimization flow for multi-fpga based prototyping that gives an end-to-end experience starting from benchmark generation to optimized inter-fpga routing. Using generic tools of the flow, ten large benchmarks are generated. Then, through a generic novel inter-fpga routing environment, effect of variation of number of fpgas as well as number of inter-fpga tracks on the performance of a target design is explored. For performance exploration and optimization, five different fpga boards are utilized where number of fpgas on board are varied from two to six. Moreover, for each board four different inter-fpga track combinations are used. Experimental results reveal that multi-fpga boards with inter-fpga tracks corresponding optimally to the cut net requirements of benchmarks under consideration give best frequency results. Furthermore, frequency comparison between different boards shows that fpga board with six fpgas gives, on average, best frequency results. Finally, we also perform frequency-price analysis which shows that board with four fpgas gives better frequency-price tradeoff as compared to other fpga boards under consideration.

关键词： field programmable gate arrays Routing Benchmark testing Computer architecture Program processors Target tracking Optimization

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Extending the Moore's law by exploring new data center architecture: Invited Paper 16

Extending the Moore's law by exploring new data center archi...

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21st IEEE/acm international symposium on Low Power Electronics and Design, ISLPED 2016

作者： Ouyang, Jian Qi, Wei Wang, Yong Baidu Baidu Campus Beijing China

ISBN: (纸本)9781450341851

In recent ten years, lots of new applications emerged, such as AI, big data and cloud. Though the workloads of these applications are very diverse, they demand huge resource of data center. In contrast, the silicon technology moves slower and slower because the Moore's law is going to the end. Consequently, the data center building from commodity hardware cannot provide enough costefficiency and power-efficiency. To meet the increasingly resource needs of emerging applications, the scale of data center is become much larger and larger. It consumes huge power and cost of hardware. From the business perspective, the slow development of hardware technology limits the value creation of emerging applications. We, Baidu, the largest search engine in China, have faced this challenge in several years ago. We find that the server number increases much faster than the scale of business. And this case is common for internet companies. Because the iteration of general processor becomes slower and slower. For example, Intel announced that the Tick-Tock production strategic was out of date in this early year. This problem drive us to look for new methods to boost business. From Internet Company's perspective, building new chips or new architecture based on its applications' characteristics makes sense. This method can break the limitation of commodity chips and commodity hardware. And according to academic and industry experiences, domain-specified architecture can achieve much better performance and power efficiency than general architecture. Consequently, we are exploring new architecture to extend Moore's law. In this paper, we present the works on exploring new architecture for data center. The data center resource includes storage, memory, computing and networking. Hence, we focus on these four areas. Firstly, we implemented SDF for large-scale distributed storage system. The SDF aims to low cost and high performance flash storage system. Secondly, we implemented SDA for dee

关键词： field programmable gate arrays (fpga)

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acm/sigda international symposium on field programmable gate arrays - fpga: Foreword

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - fpga 2013年 iii页

作者： Hutchings, Brad Betz, Vaughn Brigham Young University United States University of Toronto Canada

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