检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

779 篇 会议
30 篇 期刊文献

馆藏范围

809 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

635 篇 工学
- 529 篇 计算机科学与技术...
- 314 篇 软件工程
- 250 篇 电子科学与技术（可...
- 201 篇 电气工程
- 88 篇 信息与通信工程
- 52 篇 控制科学与工程
- 32 篇 动力工程及工程热...
- 31 篇 机械工程
- 24 篇 仪器科学与技术
- 16 篇 生物工程
- 11 篇 冶金工程
- 10 篇 建筑学
- 10 篇 土木工程
- 10 篇 化学工程与技术
- 9 篇 光学工程
- 8 篇 材料科学与工程（可...
- 8 篇 生物医学工程（可授...
- 3 篇 农业工程
228 篇 理学
- 172 篇 数学
- 47 篇 物理学
- 20 篇 统计学（可授理学、...
- 17 篇 生物学
- 10 篇 系统科学
- 8 篇 化学
55 篇 管理学
- 47 篇 管理科学与工程(可...
- 30 篇 工商管理
- 9 篇 图书情报与档案管...
14 篇 经济学
- 14 篇 应用经济学
14 篇 医学
- 13 篇 特种医学
11 篇 法学
- 9 篇 社会学
3 篇 农学
2 篇 教育学
1 篇 文学

主题

433 篇 field programmab...
232 篇 field programmab...
46 篇 hardware
32 篇 fpga
30 篇 clocks
28 篇 computer archite...
21 篇 table lookup
21 篇 delays
17 篇 random access me...
16 篇 routing
16 篇 software
15 篇 switches
12 篇 digital signal p...
11 篇 throughput
11 篇 system-on-chip
11 篇 algorithm design...
10 篇 multiplexing
10 篇 logic gates
10 篇 bandwidth
10 篇 educational inst...

机构

6 篇 univ of toronto ...
5 篇 school of comput...
5 篇 university of to...
5 篇 univ of toronto
5 篇 univ of californ...
5 篇 altera corporati...
4 篇 univ british col...
4 篇 nanyang technol ...
4 篇 dept. of cs 256-...
4 篇 department of el...
4 篇 state key lab of...
4 篇 intel corporatio...
3 篇 computer science...
3 篇 department of ee...
3 篇 department of el...
3 篇 department of el...
3 篇 xilinx inc. san ...
3 篇 technical univer...
3 篇 northwestern uni...
3 篇 nanyang technolo...

作者

20 篇 cong jason
19 篇 rose jonathan
11 篇 betz vaughn
10 篇 wawrzynek john
9 篇 dehon andré
9 篇 hauck scott
9 篇 zhang zhiru
8 篇 chen deming
7 篇 wilton steven j....
7 篇 schmit herman
7 篇 constantinides g...
7 篇 chow paul
7 篇 langhammer marti...
6 篇 cheung peter y. ...
6 篇 wilton steven j....
6 篇 pasca bogdan
6 篇 li fei
6 篇 prasanna viktor ...
5 篇 jason cong
5 篇 fahmy suhaib a.

语言

798 篇 英文
6 篇 其他
4 篇 中文
1 篇 西班牙文

检索条件"任意字段=2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013"

共 809 条记录，以下是141-150 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

An Automated Design Framework for Floating Point Scientific Algorithms using field programmable gate arrays (fpgas) (Abstract Only) 15

An Automated Design Framework for Floating Point Scientific ...

引用

Proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Michaela E. Amoo Youngsoo Kim Vance Alford Shrikant Jadhav Naser I. El-Bathy Clay S. Gloster Jr. Howard University Washington DC USA North Carolina A&T State University Greensboro NC USA

ISBN: (纸本)9781450333153

This paper presents a reconfigurable computing environment while addressing the problem of porting High Performance Computing (HPC) applications directly to field programmable gate arrays (fpgas)-based architectures. The objectives of this research are developing a comprehensive floating point library of essential functions for scientific applications; demonstrate order of magnitude speedup of reconfigurable computing applications, demonstrating the effectiveness of automated design framework for both development and test of scientific algorithms. The developed framework can be reused in various scientific applications which shares kernel functions. The study of this research has identified an exponential function as a kernel for cellular ophthalmoscopy camera processing, traffic monitoring and light wave simulation. The paper demonstrates 30x speedup of these kernels in three algorithms using its novel architecture and its automated toolset. Exponential kernel generation case study and its flexible hardware implementation on an fpga has been validated onto a Xilinx LX-100 device and the Nallatech H101-PCIXM fpga board.

关键词： floating point exponential hpc fpga

来源：评论

学校读者我要写书评

暂无评论

Acceleration of Synthetic Aperture Radar (SAR) Algorithms using field programmable gate arrays (fpgas) (Abstract Only) 15

Acceleration of Synthetic Aperture Radar (SAR) Algorithms us...

引用

Proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Youngsoo Kim William Harding Clay S. Gloster Winser Alexander North Carolina A&T State University Greensboro NC USA North Carolina State University Raleigh NC USA

ISBN: (纸本)9781450333153

Algorithms for radar signal processing, such as Synthetic Aperture Radar (SAR) are computationally intensive and require considerable execution time on a general purpose processor. Reconfigurable logic can be used to off-load the primary computational kernel onto a custom computing machine in order to reduce execution time by an order of magnitude as compared to kernel execution on a general purpose processor. Specifically, field programmable gate arrays (fpgas) can be used to house hardware-based custom implementations of these kernels to speed up these applications. In this paper, we demonstrate a methodology for algorithm acceleration. We used SAR as a case study to illustrate the tremendous potential for algorithm acceleration offered by fpgas. Initially, we profiled the SAR algorithm and implemented a homomorphic filter using a hardware implementation of the natural logarithm. Experimental results show an average speed-up of 188 when using the fpga-based hardware accelerator as opposed to using a software implementation running on a typical general purpose processor.

关键词： floating point fpga logarithmic synthetic aperture radar homomorphic

来源：评论

学校读者我要写书评

暂无评论

fpga'12 - Proceedings of the 2012 acm/sigda international symposium on field programmable gate arrays

FPGA'12 - Proceedings of the 2012 ACM/SIGDA International Sy...

引用

2012 acm/sigda international symposium on field programmable gate arrays, fpga'12

ISBN: (纸本)9781450311557

The proceedings contain 36 papers. The topics discussed include: speedy fpga-based packet classifiers with low on-chip memory requirements;a real-time stereo vision system using a tree-structured dynamic programming on fpga;incremental clustering applied to radar deinterleaving: a parameterized fpga implementation;communication visualization for bottleneck detection of high-level synthesis applications;a mixed precision Monte Carlo methodology for reconfigurable accelerator systems;saturating the transceiver bandwidth: switch fabric design on fpgas;saturating the transceiver bandwidth: switch fabric design on fpgas;limit study of energy & delay benefits of component-specific routing;impact of fpga architecture on resource sharing in high-level synthesis;and securing netlist-level fpga design through exploiting process variation and degradation.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Quantifying the cost and benefit of latency insensitive communication on fpgas 14

Quantifying the cost and benefit of latency insensitive comm...

引用

2014 acm/sigda international symposium on field programmable gate arrays, fpga 2014

作者： Murray, Kevin E. Betz, Vaughn Dept. of Electrical and Computer Engineering University of Toronto Ontario Canada

ISBN: (纸本)9781450326711

Latency insensitive communication oers many potential benets for fpga designs, including easier timing closure by enabling automatic pipelining, and easier interfacing with embedded NoCs. However, it is important to understand the costs and trade-os associated with any new design style. This paper presents optimized implementations of latency insensitive communication building blocks, quanties their overheads in terms of area and frequency, and provides guidance to designers on how to generate high-speed and areae cient latency insensitive systems.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

A power side-channel-based digital to analog converter for xilinx fpgas 14

A power side-channel-based digital to analog converter for x...

引用

2014 acm/sigda international symposium on field programmable gate arrays, fpga 2014

作者： Hutchings, Brad L. Monson, Joshua Savory, Danny Keeley, Jared Department of Electrical and Computer Engineering Brigham Young University Provo UT United States

ISBN: (纸本)9781450326711

A novel Digital to Analog Converter (DAC) modulates the overall power consumption of an fpga by disabling/enabling short circuits programmed into the interconnect. The power pin of the fpga serves as the output of the DAC. The DAC achieves high linearity and can be used to implement applications in communications, security, etc. The shortcircuit-based DAC consumes 1/3 the area of an alternative shift-register-based DAC that is presented for the sake of comparison.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

A soft error vulnerability analysis framework for xilinx fpgas 14

A soft error vulnerability analysis framework for xilinx FPG...

引用

2014 acm/sigda international symposium on field programmable gate arrays, fpga 2014

作者： Sari, Aitzan Agiakatsikas, Dimitris Psarakis, Mihalis Department of Informatics University of Piraeus Greece

ISBN: (纸本)9781450326711

Today's SRAM-based fpgas provide a reach set of computing resources which makes them attractive in demanding and critical application domains, such as avionics and space. Unfortunately, their high reliance on SRAM configuration memory arise reliability issues due to the single-event upsets (SEUs). Considering the criticality of these applications, the vulnerability analysis of fpga designs to SEUs becomes essential part of the design flow. In this context, we present an open-source framework for the soft error vulnerability analysis of Xilinx fpga devices. The proposed framework will allow researchers to evaluate their reliability-aware CAD algorithms and estimate the soft error susceptibility of the designs at early stages of the implementation flow for the latest Xilinx architectures.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

Accelerating frequent item counting with fpga 14

Accelerating frequent item counting with FPGA

引用

2014 acm/sigda international symposium on field programmable gate arrays, fpga 2014

作者： Sun, Yuliang Wang, Zilong Huang, Sitao Wang, Lanjun Wang, Yu Luo, Rong Yang, Huazhong E.E. Dept. TNLIST Tsinghua University China IBM Research-China China

ISBN: (纸本)9781450326711

Frequent item counting is one of the most important operations in time series data mining algorithms, and the space saving algorithm is a widely used approach to solving this problem. With the rapid rising of data input speeds, the most challenging problem in frequent item counting is to meet the requirement of wire-speed processing. In this paper, we propose a streaming oriented PE-ring framework on fpga for counting frequent items. Compared with the best existing fpga implementation, our basic PE-ring framework saves 50% lookup table resources cost and achieves the same throughput in a more scalable way. Furthermore, we adopt SIMD-like cascaded filter for further performance improvements, which outperforms the previous work by up to 3.24 times in some data distributions.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

Logic gates in the routing network of fpgas (Abstract Only) 15

Logic Gates in the routing network of FPGAs (Abstract Only)

引用

Proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Elias Vansteenkiste Berg Severens Dirk Stroobandt Ghent University Ghent Belgium

ISBN: (纸本)9781450333153

We propose a new kind of fpga architecture with a routing network that not only provides interconnections between the functional blocks but also performs some logic operation. More specifically we replaced the routing multiplexer node in the conventional architecture with an element that can be used as both AND gate and multiplexer. A conventional routing multiplexer node consists of a multiplexer and a two stage buffer. In our new architecture a NAND gate replaces the first inverter stage of the buffer and two multiplexers half the size of the original multiplexer replace the original multiplexer. The aim of this study is to determine if this kind of architecture is feasible and if it is worth to implement pack, placement and routing tools in the future. We developed a new technology-mapping algorithm and sized the transistors in this new architecture to evaluate the area and delay. Preliminary results indicate that the gain in logic depth and area achieved by mapping to not only LUTs but also to AND gates outweighs the overhead of introducing AND gates in the routing network with a net reduction in area-delay product of 5.6. Designs implemented on the proposed architecture would require 11.2 % more area, but they will have a 14 % decreased logic depth and the architecture has a slightly faster representative critical path. These results are preliminary because the pack, place and route routines are not implemented yet.

关键词： transistor sizing technology mapping routing nodes programmable interconnection architecture logic gates

来源：评论

学校读者我要写书评

暂无评论

Dynamic voltage & frequency scaling with online slack measurement 14

Dynamic voltage & frequency scaling with online slack measur...

引用

2014 acm/sigda international symposium on field programmable gate arrays, fpga 2014

作者： Levine, Joshua M. Stott, Edward Cheung, Peter Y. K. Department of Electrical and Electronic Engineering Imperial College London London United Kingdom

ISBN: (纸本)9781450326711

Timing margins in fpgas are already significant and as process scaling continues they will have to grow to guarantee operation under increased variation. Margins enforce worst-case operation even in typical conditions and result in devices operating more slowly and consuming more energy than necessary. This paper presents a method of dynamic voltage and frequency scaling that uses online slack measurement to determine timing headroom in a circuit while it is operating and scale the voltage and/or frequency in response. Doing so can significantly reduce power consumption or increase throughput with a minimal overhead. The method is demonstrated on a number of benchmark circuits under a range of operating conditions, constraints and optimisation targets.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

Rent's rule based fpga packing for routability optimization 14

Rent's rule based FPGA packing for routability optimization

引用

2014 acm/sigda international symposium on field programmable gate arrays, fpga 2014

作者： Feng, Wenyi Greene, Jonathan Vorwerk, Kristofer Pevzner, Val Kundu, Arun Microsemi Corporation 3870 N 1st Street San Jose CA 95134 United States

ISBN: (纸本)9781450326711

Packing is a critical step in the CAD flow for cluster-based fpga architectures, and has a significant impact on the quality of the final placement and routing results. One basic quality metric is routability. Traditionally, minimizing cut (the number of external signals) has been used as the main criterion in packing for routability optimization. This paper shows that minimizing cut is a sub-optimal criterion, and argues to use the Rent characteristic as the new criterion for fpga packing. We further propose using a recursive bipartitioning-based k-way partitioner to optimize the Rent characteristic during packing. We developed a new packer, PPack2, based on this approach. Compared to T-VPack, PPack2 achieves 35.4%, 35.6%, and 11.2% reduction in wire length, minimal channel width, and critical path delay, respectively. These improvements show that PPack2 outperforms all previous leading packing tools (including iRAC, HDPack, and the original PPack) by a wide margin.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共81页 << < 11 12 13 14 15 16 17 18 19 20 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：