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检索条件"任意字段=2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013"

共 809 条记录，以下是181-190 订阅

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Side-channel attacks on the bitstream encryption mechanism of Altera Stratix II: Facilitating black-box analysis using software reverse-engineering 13

Side-channel attacks on the bitstream encryption mechanism o...

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2013 acm/sigda international symposium on field programmable gate arrays, fpga 2013

作者： Moradi, Amir Oswald, David Paar, Christof Swierczynski, Pawel Horst Görtz Institute for IT-Security Ruhr University Bochum Bochum Germany

ISBN: (纸本)9781450318877

In order to protect fpga designs against IP theft and related issues such as product cloning, all major fpga manufacturers offer a mechanism to encrypt the bitstream used to configure the fpga. From a mathematical point of view, the employed encryption algorithms, e.g., AES or 3DES, are highly secure. However, recently it has been shown that the bitstream encryption feature of several fpga product lines is susceptible to side-channel attacks that monitor the power consumption of the cryptographic module. In this paper, we present the first successful attack on the bitstream encryption of the Altera Stratix II fpga. To this end, we reverse-engineered the details of the proprietary and unpublished Stratix II bitstream encryption scheme from the Quartus II software. Using this knowledge, we demonstrate that the full 128-bit AES key of a Stratix II can be recovered by means of side-channel analysis with 30,000 measurements, which can be acquired in less than three hours. The complete bitstream of a Stratix II that is (seemingly) protected by the bitstream encryption feature can hence fall into the hands of a competitor or criminal - possibly implying system-wide damage if confidential information such as proprietary encryption schemes or keys programmed into the fpga are extracted. In addition to lost IP, reprogramming the attacked fpga with modified code, for instance, to secretly plant a hardware trojan, is a particularly dangerous scenario for many security-critical applications. © 2013 acm.

关键词： field programmable gate arrays (fpga)

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Word-length optimization beyond straight line code 13

Word-length optimization beyond straight line code

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2013 acm/sigda international symposium on field programmable gate arrays, fpga 2013

作者： Boland, David P. Constantinides, George A. Department of Electrical and Electronic Engineering Imperial College London London United Kingdom

ISBN: (纸本)9781450318877

The silicon area benefits that result from word-length optimization have been widely reported by the fpga community. However, to date, most approaches are restricted to straight line code, or code that can be converted into straight line code using techniques such as loop-unrolling. In this paper, we take the first steps towards creating analytical techniques to optimize the precision used throughout custom fpga accelerators for algorithms that contain loops with data dependent exit conditions. To achieve this, we build on ideas emanating from the software verification community to prove program termination. Our idea is to apply word-length optimization techniques to find the minimum precision required to guarantee that a loop with data dependent exit conditions will terminate. Without techniques to analyze algorithms containing these types of loops, a hardware designer may elect to implement every arithmetic operator throughout a custom fpga-based accelerator using IEEE-754 standard single or double precision arithmetic. With this approach, the fpga accelerator would have comparable accuracy to a software implementation. However, we show that using our new technique to create custom fixed and floating point designs, we can obtain silicon area savings of up to 50% over IEEE standard single precision arithmetic, or 80% over IEEE standard double precision arithmetic, at the same time as providing guarantees that the created hardware designs will work in practice. © 2013 acm.

关键词： field programmable gate arrays (fpga)

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C-to-CoRAM: Compiling perfect loop nests to the portable CoRAM abstraction 13

C-to-CoRAM: Compiling perfect loop nests to the portable CoR...

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2013 acm/sigda international symposium on field programmable gate arrays, fpga 2013

作者： Weisz, Gabriel Hoe, James C. Computer Science Department Carnegie Mellon University Pittsburgh PA United States Electrical and Computer Engineering Department Carnegie Mellon University Pittsburgh PA United States

ISBN: (纸本)9781450318877

This paper presents initial work on developing a C compiler for the CoRAM fpga computing abstraction. The presented effort focuses on compiling fixed-bound perfect loop nests that operate on large data sets in external DRAM. As required by the CoRAM abstraction, the compiler partitions source code into two separate implementation components: (1) hardware kernel pipelines to be mapped onto the reconfigurable logic fabric;and (2) control threads that express, in a C-like language, the sequencing and coordination of data transfers between the hardware kernels and external DRAM. The compiler performs optimizations to increase parallelism and use DRAM bandwidth efficiently. It can target different fpga platforms that support the CoRAM abstraction, either natively in a future fpga or in soft-logic on today's devices. The CoRAM abstraction provides a convenient high-level compilation target to simplify the task of design optimization and system generation. The compiler is evaluated using three test programs (matrix-matrix multiplication, k-nearest neighbor, and 2D convolution) on the Xilinx ML605 and the Altera DE4. Results show that our compiler is able to target the different platforms and effectively exploit their dissimilar capacities and features. Depending on the application, the compiler-generated implementations achieve performance ranging from a factor of 4 slower to a factor of 2 faster relative to hand-designed implementations, as measured on actual hardware. © 2013 acm.

关键词： field programmable gate arrays (fpga)

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High throughput and programmable online trafficclassifier on fpga 13

High throughput and programmable online trafficclassifier on...

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2013 acm/sigda international symposium on field programmable gate arrays, fpga 2013

作者： Tong, Da Sun, Lu Matam, Kiran Prasanna, Viktor Ming Hsieh Department of Electrical Engineering University of Southern California Los Angeles CA United States

ISBN: (纸本)9781450318877

Machine learning (ML) algorithms have been shown to be effective in classifying the dynamic internet traffic today. Using additional features and sophisticated ML techniques can improve accuracy and can classify a broad range of application classes. Realizing such classifiers to meet high data rates is challenging. In this paper, we propose two architectures to realize complete online traffic classifier using flow-level features. First, we develop a traffic classifier based on C4.5 decision tree algorithm and Entropy-MDL discretization algorithm. It achieves an accuracy of 97.92% when classifying a traffic trace consisting of eight application classes. Next, we accelerate our classifier using two architectures on fpga. One architecture stores the classifier in on-chip distributed RAM. It is designed to sustain a high throughput. The other architecture stores the classifier in block RAM. It is designed to operate with small hardware footprint and thus built at low hardware cost. Experimental results show that our high throughput architecture can sustain a throughput of 550 Gbps assuming 40 Byte packet size. Our low cost architecture demonstrates a 22% better resource efficiency than the high throughput design. It can be easily replicated to achieve 449 Gbps while supporting 160 input traffic streams concurrently. Both architectures are parameterizable and programmable to support any binary-tree-based traffic classifier. We develop a tool which allows users to easily map a binary-tree-based classifier to hardware. The tool takes a classifier as input and automatically generates the Verilog code for the corresponding hardware architecture. © 2013 acm.

关键词： field programmable gate arrays (fpga)

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GROK-LAB: Generating real on-chip knowledge for intra-cluster delays using timing extraction 13

GROK-LAB: Generating real on-chip knowledge for intra-cluste...

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2013 acm/sigda international symposium on field programmable gate arrays, fpga 2013

作者： Gojman, Benjamin Nalmela, Sirisha Mehta, Nikil Howarth, Nicholas DeHon, André Department of Computer and Information Systems University of Pennsylvania 3330 Walnut Street Philadelphia PA 19104 United States Juniper Networks 10 Technology Park Drive Westford MA 01886 United States Department of Computer Science California Institute of Technology MC 305-16 1200 E. California Blvd. Pasadena CA 91125 United States Department of Electrical and Systems Engineering University of Pennsylvania 200 S. 33rd St. Philadelphia PA 19104 United States

ISBN: (纸本)9781450318877

Timing Extraction identifies the delay of fine-grained components within an fpga. From these computed delays, the delay of any path can be calculated. Moreover, a comparison of the fine-grained delays allows a detailed understanding of the amount and type of process variation that exists in the fpga. To obtain these delays, Timing Extraction measures, using only resources already available in the fpga, the delay of a small subset of the total paths in the fpga. We apply Timing Extraction to the Logic Array Block (LAB) on an Altera Cyclone III fpga to obtain a view of the delay down to near individual LUT granularity, characterizing components with delays on the order of a few hundred picoseconds with a resolution of ±3.2 ps. This information reveals that the 65 nm process used has, on average, random variation of σ/μ = 4.0% with components having an average maximum spread of 83 ps. Timing extraction also shows that as VDD decreases from 1.2 V to 0.9 V in a Cyclone IV 60 nm fpga, paths slow down and variation increases from σ/μ = 4.3% to σ/μ = 5.8%, a clear indication that lowering VDD magnifies the impact of random variation. © 2013 acm.

关键词： field programmable gate arrays (fpga)

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An fpga based parallel architecture for music melody matching 13

An FPGA based parallel architecture for music melody matchin...

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2013 acm/sigda international symposium on field programmable gate arrays, fpga 2013

作者： Wang, Hao Liu, Jyh-Charn Department of Computer Science and Engineering Texas A and M University College Station TX 77840 United States

ISBN: (纸本)9781450318877

We propose an fpga-based high performance parallel architecture for music retrieval through singing. The database consists of monophonic MIDI files which are modeled into strings, and the user sung query is modeled as a set of regular expressions (regexp), with consideration of possible key transpositions and tempo variations to tolerate imperfectly sung queries. An approximate regexp matching algorithm is developed to calculate the similarity between a regexp and a string, using edit distance as the metrics. The algorithm supports user sung queries starting anywhere in the database song, not necessarily from the beginning. Using the proposed formal models and algorithms, the similarity between the user sung query and each song in the database can be evaluated and the top-10 most similar results will be reported. We designed the approximate regexp matching algorithm in such way that all terms of the regexp can execute concurrently, which perfectly fits the massive parallelism provided by fpga. The fpga implemented melody matching engine (MME) is a parameterized modular architecture that can be reconfigured to implement different regexps by simply updating their parameter registers, and can therefore avoid the time-consuming code re-synthesis. MME also includes an on-board DDR2 memory to store the database, so that they can be read in to calculate edit distances locally on the board. This way, each MME forms a self-contained system and multiple MMEs can be clustered to increase parallel processing power, with virtually no overhead. MME is evaluated using the query corpus of ThinkIT with 355 sung files and database of 5563 MIDI files. It achieves a top-10 hit rate of 90.7% and a runtime of 19.4 seconds, averaging 54.6 milliseconds for a single query. MME achieves significant speedup over software-based systems while providing the same level of flexibility. © 2013 acm.

关键词： field programmable gate arrays (fpga)

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fpga'11 - Proceedings of the 2011 acm/sigda international symposium on field programmable gate arrays

FPGA'11 - Proceedings of the 2011 ACM/SIGDA International Sy...

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2011 19th acm/sigda international symposium on field programmable gate arrays, fpga'11

ISBN: (纸本)9781450305549

The proceedings contain 37 papers. The topics discussed include: comparing fpga vs. custom CMOs and the impact on processor microarchitecture;VEGAS: soft vector processor with scratchpad memory;leap scratchpads: automatic memory and cache management for reconfigurable logic;NETTM: faster and easier synchronization for soft multicores via transactional memory;LegUp: high-level synthesis for fpga-based processor/accelerator systems;automatic SoC design flow on many-core processors: a software hardware co-design approach for fpgas;Torc: towards an open-source tool flow;fpgaSort: a high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sorting;a platform for high level synthesis of memory-intensive image processing algorithms;energy-efficient specialization of functional units in a coarse-grained reconfigurable array;and DEEP: an iterative fpga-based many-core emulation system for chip verification and architecture research.

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Pipeline template and scheduling algorithm for mapping multiple loop nests on fpga with limited resources 13

Pipeline template and scheduling algorithm for mapping multi...

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23rd acm international Conference of the Great Lakes symposium on VLSI, GLSVLSI 2013

作者： Dong, Yazhuo Zhan, Wu Ye, Xiqing Naval Academy of Armament No. 3 Wanshou Street Haidian area Beijing City 100036 China

ISBN: (纸本)9781450319027

There are large numbers of high-level algorithms consisting of multiple loop nests in image compression, pattern recognition and digital signal processing. fpga provides a convenient and flexible solution to speed up these loop-intensive algorithms. However, fpga reconfiguration which needs a long time is inevitable when switching between the loop nests. This paper presents a parameterized pipeline template to execute all the loop nests in sequence without fpga reconfiguration. Five steps are designed to decide the parameters. Experiments show that the pipeline template can achieve a comparative execution cycles for a loop comparing with the special hardware structure. © 2013 Authors.

关键词： field programmable gate arrays (fpga)

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Power estimation tool for system on programmable chip based platforms (abstract only) 14

Power estimation tool for system on programmable chip based ...

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Proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Santhosh Kumar Rethinagiri Oscar Palomar Adrian Cristal Osman Unsal BSC - Microsoft Research Center Barcelona Spain BSC - Mircrosoft Research Center Barcelona Spain

ISBN: (纸本)9781450326711

The ever increasing complexity of the applications result in the development of power hungry processors. There is a scarcity of standalone tools that have a good trade off between estimation speed and accuracy to estimate power/energy at an earlier phase of design flow. There are very few tools that addresses the design space exploration issue based on power and energy. In this paper, we propose a virtual platform based standalone power and energy estimation tool for System-on-programmable Chip (SoPC) embedded platforms, which is independent of in-house tools. There are two steps involved in this tool development. The first step is power model generation. For the power model development, we used functional parameters to set up generic power models for the different parts of the system. This is a onetime activity. In the second step, a simulation based virtual platform framework is developed to evaluate accurately the activities used in the related power models developed in the first step. The combination of the two steps lead to a hybrid power estimation, which gives a better trade-off between accuracy and speed. The proposed tool has several benefits: it considers the power consumption of the embedded system in its entirety and leads to accurate estimates without a costly and complex material. The proposed tool is also scalable for exploring complex embedded multi-core *** effectiveness of our proposed tool is validated through dualcore RISC processor designed around the fpga board and extended to accommodate futuristic multi-core processors for a reliable energy based design space exploration. The accuracy of our proposed tool is evaluated by using a variety of industrial benchmarks such as Multimedia, EEMBC and SPEC2006. Estimated power values are compared to real board measurements and also to McPAT. Our obtained power/energy estimation results provide less than 9% of error for heterogeneous MPSoC based system and are 200% faster compared to other

关键词： power/energy estimation fpga systemc heterogeneous architecture asic tlm speedup multicore functional power models design space exploration virtual platform accuracy

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Improving high level synthesis optimization opportunity through polyhedral transformations 13

Improving high level synthesis optimization opportunity thro...

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2013 acm/sigda international symposium on field programmable gate arrays, fpga 2013

作者： Zuo, Wei Liang, Yun Li, Peng Rupnow, Kyle Chen, Deming Cong, Jason Center for Energy-Efficient Computing and Applications School of EECS Peking University China University of Illinois Urbana-Champaign IL United States Advanced Digital Science Center Singapore Singapore Computer Science Department University of California Los Angeles CA United States School of Information and Electronics Beijing Institute of Technology China

ISBN: (纸本)9781450318877

High level synthesis (HLS) is an important enabling technology for the adoption of hardware accelerator technologies. It promises the performance and energy efficiency of hardware designs with a lower barrier to entry in design expertise, and shorter design time. State-of-the-art high level synthesis now includes a wide variety of powerful optimizations that implement efficient hardware. These optimizations can implement some of the most important features generally performed in manual designs including parallel hardware units, pipelining of execution both within a hardware unit and between units, and fine-grained data communication. We may generally classify the optimizations as those that optimize hardware implementation within a code block (intra-block) and those that optimize communication and pipelining between code blocks (inter-block). However, both optimizations are in practice difficult to apply. Real-world applications contain data-dependent blocks of code and communicate through complex data access patterns. Existing high level synthesis tools cannot apply these powerful optimizations unless the code is inherently compatible, severely limiting the optimization opportunity. In this paper we present an integrated framework to model and enable both intra- and inter-block optimizations. This integrated technique substantially improves the opportunity to use the powerful HLS optimizations that implement parallelism, pipelining, and fine-grained communication. Our polyhedral model-based technique systematically defines a set of data access patterns, identifies effective data access patterns, and performs the loop transformations to enable the intra- and inter-block optimizations. Our framework automatically explores transformation options, performs code transformations, and inserts the appropriate HLS directives to implement the HLS optimizations. Furthermore, our framework can automatically generate the optimized communication blocks for fine-grained communica

关键词： field programmable gate arrays (fpga)

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