检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

779 篇 会议
30 篇 期刊文献

馆藏范围

809 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

635 篇 工学
- 529 篇 计算机科学与技术...
- 314 篇 软件工程
- 250 篇 电子科学与技术（可...
- 201 篇 电气工程
- 88 篇 信息与通信工程
- 52 篇 控制科学与工程
- 32 篇 动力工程及工程热...
- 31 篇 机械工程
- 24 篇 仪器科学与技术
- 16 篇 生物工程
- 11 篇 冶金工程
- 10 篇 建筑学
- 10 篇 土木工程
- 10 篇 化学工程与技术
- 9 篇 光学工程
- 8 篇 材料科学与工程（可...
- 8 篇 生物医学工程（可授...
- 3 篇 农业工程
228 篇 理学
- 172 篇 数学
- 47 篇 物理学
- 20 篇 统计学（可授理学、...
- 17 篇 生物学
- 10 篇 系统科学
- 8 篇 化学
55 篇 管理学
- 47 篇 管理科学与工程(可...
- 30 篇 工商管理
- 9 篇 图书情报与档案管...
14 篇 经济学
- 14 篇 应用经济学
14 篇 医学
- 13 篇 特种医学
11 篇 法学
- 9 篇 社会学
3 篇 农学
2 篇 教育学
1 篇 文学

主题

433 篇 field programmab...
232 篇 field programmab...
46 篇 hardware
32 篇 fpga
30 篇 clocks
28 篇 computer archite...
21 篇 table lookup
21 篇 delays
17 篇 random access me...
16 篇 routing
16 篇 software
15 篇 switches
12 篇 digital signal p...
11 篇 throughput
11 篇 system-on-chip
11 篇 algorithm design...
10 篇 multiplexing
10 篇 logic gates
10 篇 bandwidth
10 篇 educational inst...

机构

6 篇 univ of toronto ...
5 篇 school of comput...
5 篇 university of to...
5 篇 univ of toronto
5 篇 univ of californ...
5 篇 altera corporati...
4 篇 univ british col...
4 篇 nanyang technol ...
4 篇 dept. of cs 256-...
4 篇 department of el...
4 篇 state key lab of...
4 篇 intel corporatio...
3 篇 computer science...
3 篇 department of ee...
3 篇 department of el...
3 篇 department of el...
3 篇 xilinx inc. san ...
3 篇 technical univer...
3 篇 northwestern uni...
3 篇 nanyang technolo...

作者

20 篇 cong jason
19 篇 rose jonathan
11 篇 betz vaughn
10 篇 wawrzynek john
9 篇 dehon andré
9 篇 hauck scott
9 篇 zhang zhiru
8 篇 chen deming
7 篇 wilton steven j....
7 篇 schmit herman
7 篇 constantinides g...
7 篇 chow paul
7 篇 langhammer marti...
6 篇 cheung peter y. ...
6 篇 wilton steven j....
6 篇 pasca bogdan
6 篇 li fei
6 篇 prasanna viktor ...
5 篇 jason cong
5 篇 fahmy suhaib a.

语言

798 篇 英文
6 篇 其他
4 篇 中文
1 篇 西班牙文

检索条件"任意字段=2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013"

共 809 条记录，以下是221-230 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Embedded Reconfigurable Augmented DC-DC Boost Converter for Fast Transient Recovery

Embedded Reconfigurable Augmented DC-DC Boost Converter for ...

引用

26th international Conference on VLSI Design Held Concurrently with 12th international Conference on Embedded Systems Design

作者： Mishra, Neeraj Jha, Niraj Kapat, Santanu Patra, Amit Indian Inst Technol Dept Elect Engn Kharagpur 721302 W Bengal India

ISBN: (纸本)9780769548890

A DC-DC boost converter is widely used for power management applications. However, the right-half-plane zero effect still remains a bottleneck for fast transient recovery. This paper is intended to propose an embedded reconfigurable boost converter solution with ultra-fast transient recovery through near-lossless augmentation. This augmentation branch requires an extra synchronous phase in parallel, comprising a small inductor and a half-bridge switch cell. This branch is activated only during large-signal transient recovery. The original converter topology is restored for steady state operations, thereby improving the overall efficiency. A prototype augmented boost converter is tested, and the proposed controller is implemented using an fpga device. The extra branch closely nullifies current and voltage overshoot/undershoots. It is also expected to have almost no impact on efficiency.

关键词： DC-DC power convertors field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Intellectual Property Protection for fpga Designs with Soft Physical Hash Functions: First Experimental Results

Intellectual Property Protection for FPGA Designs with Soft ...

引用

IEEE international symposium on Hardware-Oriented Security and Trust (HOST)

作者： Kerckhof, Stephanie Durvaux, Francois Standaert, Francois-Xavier Gerard, Benoit Catholic Univ Louvain ICTEAM ELEN Crypto Grp Louvain Belgium

ISBN: (纸本)9781479906017;9781479905591

The use of Soft Physical Hash (SPH) functions has been recently introduced as a flexible and efficient way to detect Intellectual Property (IP) cores in microelectronic systems. Previous works have mainly investigated software IP to validate this approach. In this paper, we extend it towards the practically important case of fpga designs. Based on experiments, we put forward that SPH functions-based detection is a promising and low-cost solution for preventing anti-counterfeiting, as it does not require any a-priori modification of the design flow. In particular, we illustrate its performances with stand-alone fpga designs, re-synthetized fpga designs, and in the context of parasitic IPs running in parallel.

关键词： cryptography field programmable gate arrays file organisation integrated circuit design logic circuits logic design microprocessor chips

来源：评论

学校读者我要写书评

暂无评论

A High Speed Configurable fpga Architecture For K-mean Clustering

A High Speed Configurable FPGA Architecture For K-mean Clust...

引用

IEEE international symposium on Circuits and Systems (ISCAS)

作者： Kutty, Jithin Sankar Sankaran Boussaid, Farid Amira, Abbes Univ Western Australia Sch Elect & Comp Engn Perth WA 6009 Australia W Scotland Univ Sch Comp Paisley England

ISBN: (纸本)9781467357623;9781467357609

This paper presents a high speed configurable fpga architecture for k-means clustering. The proposed architecture is highly pipelined, parallel and fully configurable. It can achieve an operating frequency of 400 MHz, which is at least three times faster than prior works. The proposed architecture addresses the high speed and throughput requirements of machine vision, multi-media and data mining applications.

关键词： field programmable gate arrays pattern clustering

来源：评论

学校读者我要写书评

暂无评论

An fpga-Based Test Platform for Analyzing Data Retention Time Distribution of DRAMs

An FPGA-Based Test Platform for Analyzing Data Retention Tim...

引用

international symposium on VLSI Design, Automation, and Test (VLSI-DAT)

作者： Hou, Chih-Sheng Li, Jin-Fu Lo, Chih-Yen Kwai, Ding-Ming Chou, Yung-Fa Wu, Cheng-Wen Natl Cent Univ Dept Elect Engn Jhongli 320 Taiwan Ind Technol Res Inst Informat & Commun Res Labs Hsinchu 310 Taiwan

ISBN: (纸本)9781467344364

Data retention time distribution of a dynamic random access memory (DRAM) has a heavy impact on its yield, power, and performance. Accurate and detailed information of data retention time distribution thus is very important for the DRAM designer and user. This paper proposes an fpga-based test platform for analyzing the data retention time distribution of a DRAM. Based on the test platform, a test flow is also proposed to classify the DRAM cells with different data retention times with respect to different supply voltage and temperature. We have demonstrated the test platform and test flow using a Micron 2Gb DRAM.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

IEEE 1588 Transparent Clock Architecture for fpga-based Network Devices

IEEE 1588 Transparent Clock Architecture for FPGA-based Netw...

引用

IEEE international symposium on Industrial Electronics (ISIE)

作者： Moreira, Naiara Astarloa, Armando Lazaro, Jesus Garcia, Alain Ormaetxea, Enekoitz Univ Basque Country UPV EHU Bilbao 48013 Spain

ISBN: (纸本)9781467351942;9781467351928

Apart from traditional test and measurement systems where clock synchronization is required, new emerging application areas like SmartGrids and 4G cellular mobile backhaul networks present strong timing constraints in terms of precise time synchronization. Precision Time Protocol (PTP), as defined in IEEE 1588 standard, offers sub-microsecond synchronization using conventional Ethernet networks. Thus, its acceptance is heavily increasing. However, the protocol performance was reduced in large cascaded networks with varying latencies. This drawback was later softened by the second version of the standard with the introduction of the Transparent Clock (TC) device. In this paper, a general overview of PTPv2 and the utilization of TCs is outlined. The main contribution is a new TC architecture for a fpga-based network device that benefits from reconfigurable devices flexibility.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

An Improved Method of fpga-based TDC for Time-of-Flight PET

An Improved Method of FPGA-based TDC for Time-of-Flight PET

引用

60th IEEE Nuclear Science symposium (NSS) / Medical Imaging Conference (MIC) / 20th international Workshop on Room-Temperature Semiconductor X-ray and Gamma-ray Detectors

作者： Kim, Daehoon Choi, Yong Lee, Sangwon Sogang Univ Dept Elect Engn Mol Imaging Res & Educ MiRe Lab Seoul South Korea

ISBN: (纸本)9781479905348

Time-to-digital converter (TDC) implemented in field-programmable-gate arrays (fpgas) with the use of tapped delay line (TDL) methods using dedicated carry chain structures has been utilized to obtain precise timing information for time-of-flight (TOF) PET. However, such chain-structural fpga-based TDCs suffer from the uneven tap delay, which is one of the main limitations for enhancing the timing performance of TDC. To subdivide the non-uniform tap delay, we propose a TDC with dual-TDL having different starting points. In a fpga (Spartan-6 LX45, Xilinx USA), two delay lines for a channel were implemented close to the fpga input pad and one of two delay lines had starting point in further slice from the input pad. In calibration process, the size of wide time bins from the uneven tap delay was reduced using different characteristics of two delay lines. In simulation study, the average time bin size was reduced from 24.7 ps to 12.6 ps and the size of widest time bin was reduced from 168 ps to 56 ps. The performance of the proposed TDC was measured with two input pulses that were generated from a pulse generator. The timing resolution of the TDC was 35 ps FWHM which was improved compared to single-TDL TDC pair (56 ps FWHM). The results of this preliminary study present dual-TDL calibration can effectively improve the time resolution of TDC. The subject of further study will be to extend the number of TDC channels in a fpga for TOF-PET applications.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

Evaluating a low cost robustness improvement in SRAM-based fpgas

Evaluating a low cost robustness improvement in SRAM-based F...

引用

2013 IEEE 19th international On-Line Testing symposium, IOLTS 2013

作者： Jrad, M.Ben Leveugle, R. 46 Avenue Félix Viallet 38031 Grenoble Cedex France

Soft errors in the configuration memory of SRAM-based fpgas cause significant application disturbances. We demonstrate on Xilinx and Altera fpgas the feasibility of a very low cost and automated mitigation approach an... 详细信息

ISBN: (纸本)9781479906628

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

A study of the partitioned dynamic programming algorithm for genome comparison in fpga

A study of the partitioned dynamic programming algorithm for...

引用

IEEE international symposium on Circuits and Systems (ISCAS)

作者： Hu, Yuanqi Georgiou, Pantelis Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn Ctr Bioinspired Technol Inst Biomed Engn London SW7 2AZ England

ISBN: (纸本)9781467357623;9781467357609

This paper explores the potential of partitioning the dynamic programming algorithm to utilise the capabilities of fpga platforms for parallel genome sequence comparison and assembly. We use this to solve the prefix-suffix approximate matching problem to find overlaps between DNA strands in a given sequence. This is achieved by partitioning the basic dynamic programming (DP) algorithm into a series of discrete sub-DP calculations. Analysis of the error rate as a result of this partitioning by applying random sequences as input data is shown, and simulation results confirm good matching with the original algorithm with an error of less that 1.5% in the worst case. Optimisation for array implementation in fpga is shown and linear scalability for larger arrays is proven. Simulation results of the whole system confirm 98.8% similarity of the overlap adjacent matrix between error and error-free data.

关键词： DNA biology computing dynamic programming error analysis field programmable gate arrays genomics

来源：评论

学校读者我要写书评

暂无评论

Enabling Difference-Based Dynamic Partial Self Reconfiguration for Large Differences

Enabling Difference-Based Dynamic Partial Self Reconfigurati...

引用

8th IEEE international Design and Test symposium (IDT)

作者： Goren, Sezer Ozkurt, Ozgur Turk, Yusuf Yildiz, Abdullah Ugurdag, H. Fatih Yeditepe Univ Dept Comp Engn Istanbul Turkey Vestek R&D Istanbul Turkey Ozyegin Univ Dept Elect & Elect Engn Istanbul Turkey

ISBN: (纸本)9781479935253

This paper presents a new Dynamic Partial Self Reconfiguration (DPSR) flow for Xilinx fpgas. Leveraging the Xilinx fpga Editor and Plan Ahead tools, we provide two implementation approaches that enable partial reconfiguration for large configuration changes without Xilinx's paid tool. The flow is difference-based but still allows a modular design, which is made up of Partial Reconfiguration (PR) modules and a static design. It works regardless of the amount of difference between PR modules. We call this flow DPSR-LD, where LD stands for Large Differences. DPSR-LD is an enabler especially for Spartan-6 fpga family, as Xilinx currently supports PR on Spartan-6 only through the difference-based flow and only for small differences. DPSR-LD also includes an ICAP controller that makes DPSR possible and offers bitstream compression.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

Built-in Self-Repair in a 3D Die Stack Using programmable Logic

Built-in Self-Repair in a 3D Die Stack Using Programmable Lo...

引用

IEEE international symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

作者： Nepal, Kundan Shen, Xi Dworak, Jennifer Manikas, Theodore Bahar, R. Iris Univ St Thomas Sch Engn St Paul MN 55105 USA Southern Methodist Univ Dept Comp Sci & Engn Dallas TX USA Brown Univ Sch Engn Providence RI 02912 USA

ISBN: (纸本)9781479915859;9781479915835

3D stacked integrated circuits hold great promise for increasing system performance, but difficulties in testing dies and assembling a 3D stack are leading to yield issues and slowing the large scale manufacture of these devices. We propose helping to mitigate these issues by repairing the stack with programmable logic in fpgas that have already been included in the stack for other purposes. Specifically, we propose bypassing the defective portion of a die by replacing the defective functionality with functionality on the fpga. In this paper, we focus on the replacement of selected defective functional units in an out-of-order microprocessor. Our simulation results show that not only can we salvage a device that would otherwise have to be discarded, but creating multiple copies of the defective partition in the fpga can allow us to regain performance even when the latency of the units in the fpga is longer than that of the original defective copy.

关键词： built-in self test field programmable gate arrays microassembling microprocessor chips programmable logic devices three-dimensional integrated circuits

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共81页 << < 19 20 21 22 23 24 25 26 27 28 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：