检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

779 篇 会议
30 篇 期刊文献

馆藏范围

809 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

635 篇 工学
- 529 篇 计算机科学与技术...
- 314 篇 软件工程
- 250 篇 电子科学与技术（可...
- 201 篇 电气工程
- 88 篇 信息与通信工程
- 52 篇 控制科学与工程
- 32 篇 动力工程及工程热...
- 31 篇 机械工程
- 24 篇 仪器科学与技术
- 16 篇 生物工程
- 11 篇 冶金工程
- 10 篇 建筑学
- 10 篇 土木工程
- 10 篇 化学工程与技术
- 9 篇 光学工程
- 8 篇 材料科学与工程（可...
- 8 篇 生物医学工程（可授...
- 3 篇 农业工程
228 篇 理学
- 172 篇 数学
- 47 篇 物理学
- 20 篇 统计学（可授理学、...
- 17 篇 生物学
- 10 篇 系统科学
- 8 篇 化学
55 篇 管理学
- 47 篇 管理科学与工程(可...
- 30 篇 工商管理
- 9 篇 图书情报与档案管...
14 篇 经济学
- 14 篇 应用经济学
14 篇 医学
- 13 篇 特种医学
11 篇 法学
- 9 篇 社会学
3 篇 农学
2 篇 教育学
1 篇 文学

主题

433 篇 field programmab...
232 篇 field programmab...
46 篇 hardware
32 篇 fpga
30 篇 clocks
28 篇 computer archite...
21 篇 table lookup
21 篇 delays
17 篇 random access me...
16 篇 routing
16 篇 software
15 篇 switches
12 篇 digital signal p...
11 篇 throughput
11 篇 system-on-chip
11 篇 algorithm design...
10 篇 multiplexing
10 篇 logic gates
10 篇 bandwidth
10 篇 educational inst...

机构

6 篇 univ of toronto ...
5 篇 school of comput...
5 篇 university of to...
5 篇 univ of toronto
5 篇 univ of californ...
5 篇 altera corporati...
4 篇 univ british col...
4 篇 nanyang technol ...
4 篇 dept. of cs 256-...
4 篇 department of el...
4 篇 state key lab of...
4 篇 intel corporatio...
3 篇 computer science...
3 篇 department of ee...
3 篇 department of el...
3 篇 department of el...
3 篇 xilinx inc. san ...
3 篇 technical univer...
3 篇 northwestern uni...
3 篇 nanyang technolo...

作者

20 篇 cong jason
19 篇 rose jonathan
11 篇 betz vaughn
10 篇 wawrzynek john
9 篇 dehon andré
9 篇 hauck scott
9 篇 zhang zhiru
8 篇 chen deming
7 篇 wilton steven j....
7 篇 schmit herman
7 篇 constantinides g...
7 篇 chow paul
7 篇 langhammer marti...
6 篇 cheung peter y. ...
6 篇 wilton steven j....
6 篇 pasca bogdan
6 篇 li fei
6 篇 prasanna viktor ...
5 篇 jason cong
5 篇 fahmy suhaib a.

语言

798 篇 英文
6 篇 其他
4 篇 中文
1 篇 西班牙文

检索条件"任意字段=2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013"

共 809 条记录，以下是241-250 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

An fpga-based Point Target Detection System using Morphological Clutter Elimination

An FPGA-based Point Target Detection System using Morphologi...

引用

IEEE international symposium on Circuits and Systems (ISCAS)

作者： Huang, Chun-Hsian Natl Taitung Univ Dept Comp Sci & Informat Engn Taitung Taiwan

ISBN: (纸本)9781467357623;9781467357609

In this work, we propose a point target detection system (PTDS) based on the fpga technology. Instead of adopting the traditional filter-based methods, in the PTDS, we design a pipelined morphological clutter elimination (PMCE) hardware design with the ability of pipeline and parallel computing. Using the PMCE hardware design, the infrared images can be processed in real-time, which thus enhances system performance significantly. To provide seamless data transfers between the PMCE hardware design and the microprocessor, a hardware/software interface component is also designed in the PTDS. Experiments with an application of point target detection for processing real-time 320 x 240 pixel infrared images demonstrate that the PTDS can speed up 18 times the execution time required by using the software method.

关键词： clutter field programmable gate arrays infrared imaging microprocessor chips object detection

来源：评论

学校读者我要写书评

暂无评论

Implementation of one level 2D DWT using multiplier less modified flipping architecture

Implementation of one level 2D DWT using multiplier less mod...

引用

7th Asia international Conference on Mathematical Modelling and Computer Simulation, AMS 2013

作者： Vijay, Parvatham Gopalakrishnan, Seetharaman Department of ECE Anna University Tiruchirappalli India Oxford Engineering College Tiruchirappalli India

ISBN: (纸本)9780769551012

This paper presents a novel architecture for the implementation of one level 2D DWT. The architecture is designed by using shifters and adders without using multipliers. The structure is designed for modified flipping based DWT. The System On programmable Chip approach (SPOC) is adopted for the implementation of one level 2D DWT on Alter a field programmable gate Array CYCLONE II EP2C35F672C6 kits with NIOS-II soft-core processor. From the implementation results, it is verified that, the proposed multiplier less modified flipping structure operated with higher speed by 7.39% and reduces the logical elements by 22.98% compared with modified flipping structure. The power dissipation is also reduced by 3.3% compared to modified flipping structure. © 2013 IEEE.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

A Stroboscopic Approach To Surface Acoustic Wave Delay Line Interrogation

A Stroboscopic Approach To Surface Acoustic Wave Delay Line ...

引用

Joint European Frequency and Time Forum / international Frequency Control symposium (EFTF/IFC)

作者： Chretien, N. Friedt, J. -M. Martin, G. Ballandras, S. SENSeOR Besancon France FEMTO ST CNRS UMR 6174 Time & frequency Besancon France

ISBN: (纸本)9781479903429

A pulsed RADAR approach is investigated to probe acoustic delay lines used as passive sensors. In order to comply with the requirements of compact, low power receiver electronics, a stroboscopic equivalent time sampling approach is demonstrated. A strategy for generating high resolution time delays while allowing for long interrogation durations (up to 5 mu s) is implemented by combining an fpga-based delay generator with commercially available programmable digital delay lines. The measurement sequence of generating interleaved combs is due to the long delay line reconfiguration duration (SPI communication) with respect to the coarse comb (fpga based counter). The response of the sensor is recorded and processed to acquire the coarse acoustic velocity information through magnitude measurement, and an accurate physical quantity estimate is computed thanks to the phase information. We demonstrate an improved software measurement strategy which prevents the slow process associated with a stroboscopic approach and allows to reach refresh rates of up to 20 kHz when probing an acoustic tag for a physical property measurement, while keeping the hardware to a bare minimum.

关键词： acoustic delay lines field programmable gate arrays radar signal processing surface acoustic wave sensors

来源：评论

学校读者我要写书评

暂无评论

A fine-grained dependable optically reconfigurable gate array as a multi-soft-core processor platform

A fine-grained dependable optically reconfigurable gate arra...

引用

2013 IEEE 7th international symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013

作者： Moriwaki, Retsu Watanabe, Minoru Electrical and Electronic Engineering Shizuoka University 3-5-1 Johoku Hamamatsu Shizuoka 432-8561 Japan

ISBN: (纸本)9780768550862

Optically reconfigurable gate arrays (ORGAs) have been developed as high-speed reconfigurable fine grained gate arrays that can accommodate implementation of a multi-soft-core processor. An ORGA's programmable gate array can be reconfigured in nanosecond-order with one of more than 256 reconfiguration contexts. Its high-speed dynamic reconfiguration capability is suitable for dynamically changing the functions of a multi-core processor. In addition to that beneficial feature, ORGAs have high dependability against space radiation since the ORGA can be reconfigured with an error-included configuration context. In this paper, while maintaining its highly dependable capability, a more advanced dependability-increasing technique using a negative logic implementation is proposed. The dependability of data on a holographic memory depends on the number of bright bits or the binary state H included in a configuration context. If the number of bright bits in a configuration context can be decreased, then the configuration dependability can also be increased. The proposed optical configuration dependability-increasing technique of a negative logic implementation can decrease the number of bright bits in a configuration context. This technique can raise the ORGA's configuration dependability level even further. This paper describes an experimental demonstration of the usefulness of the proposed technique. © 2013 IEEE.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

fpga implementation for a recursive least square algorithm

FPGA implementation for a recursive least square algorithm

引用

2013 2nd international symposium on Instrumentation and Measurement, Sensor Network and Automation, IMSNA 2013

作者： Liang, Peng Sun, Guocang Deng, Haihua Ming, Chen Wuhan Second Ship Design and Research Institute Wuhan Hubei 430064 China

ISBN: (纸本)9781479927166

A recursive least square algorithm is implemented in this paper. Memory Nonlinearity of digital receiver is compensated by using a blind identification algorithm based on nonlinear model. A least-squared blind identification criterion to minimize all the energy of the nonlinearity in the receiver's output signal is implemented under circumstances of not knowing the information of the receiver's input signal. The orders and memory depths of the Volterra model are tested and updated automatically. A double-precision arbitrary-dimensional matrix inversion module is implemented in the requirement of the least-squared method. The digital post calibration processes in real-time. Experimental results on the actual nonlinear circuit illustrate the validity of the implemented technique. © 2013 IEEE.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

Stacking of known good rebuilt wafers for high performance memory and SiP

Stacking of known good rebuilt wafers for high performance m...

引用

46th Annual IMAPS international symposium on Microelectronics, IMAPS 2013

作者： Couderc, Pascal Noiray, Jerome Val, Christian 3D PLUS 408 Rue Hélène Boucher 78532 BUC France

ISBN: (纸本)9781629938240

Based on Wire-free Die on Die disruptive technology (WDoD™), high density memory can be manufactured in a small form factor package size. Stacking known good rebuilt wafers allows high yields while integrating high performance devices. Dual die (DD) and Quad die (QD) DDR3 memories exhibit outstanding performance and show the path to highly densified System in Package (SiP) for Medical, Defense and Industrial markets.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

A fast CAM-based image matching system on fpga

A fast CAM-based image matching system on FPGA

引用

2013 IEEE international symposium on Circuits and Systems, ISCAS 2013

作者： Le, Duc-Hung Cao, Tran Bao Thuong Inoue, Katsumi Pham, Cong-Kha University of Electro-Communications Tokyo Japan Advanced Original Technologies Chiba Japan University of Science Ho Chi Minh City Viet Nam

ISBN: (纸本)9781467357609

A CAM-based (Content Addressable Memory) image matching system is implemented on hardware system using fpga. The system has simple structure, does not employ any Central Processor Units (CPUs) as well as complicated computations. The authors take advantages of CAM which has an ability of parallel multi-match mode for designing the system. Thus increases the matching performance of the system. The system is applied for exact image matching or approximate image matching with various required search patterns without using search principles. In this paper, the authors present the system for fast image matching applications on 2-D data. © 2013 IEEE.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

High-resolution multichannel Time-to-Digital Converter core implemented in fpga for ToF measurements in SiPM-PET

High-resolution multichannel Time-to-Digital Converter core ...

引用

60th IEEE Nuclear Science symposium (NSS) / Medical Imaging Conference (MIC) / 20th international Workshop on Room-Temperature Semiconductor X-ray and Gamma-ray Detectors

作者： Torres, J. Aguilar, A. Garcia-Olcina, R. Martos, J. Soret, J. Gonzalez, A. J. Conde, P. Hernandez, L. Sanchez, F. Benlloch, J. M. Univ Valencia Commun & Digital Syst Design Grp DSDC E-46003 Valencia Spain

ISBN: (纸本)9781479905348

In this contribution, Coincidence Resolving Time (CRT) results with the developed multichannel fpga-TDC are showed as a function of different configurations for both, the sensor bias voltage and the digitizer threshold. The dependence of the CRT with the sensor matrix temperature, the amount of SiPM active area and the crystal type are also analyzed. Preliminary measurements carried out with a crystal array of 2 mm pixel size and 10 mm height have shown time resolutions for the entire 144 SiPM two-detectors ensemble as good as 800 ps.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

fpga-based high-speed authenticated encryption system

FPGA-based high-speed authenticated encryption system

引用

20th IFIP/IEEE international Conference on Very Large Scale Integration, VLSI-SoC 2012

作者： Muehlberghuber, Michael Keller, Christoph Gürkaynak, Frank K. Felber, Norbert ETH Zurich Gloriastrasse 35 Zurich8092 Switzerland

ISBN: (纸本)9783642450723

The Advanced Encryption Standard (AES) running in the Galois/Counter Mode of Operation represents a de facto standard in the field of hardware-accelerated, block-cipher-based high-speed authenticated encryption (AE) systems. We propose hardware architectures supporting the Ethernet standard IEEE 802.3ba utilizing different cryptographic primitives suitable for AE applications. Our main design goal was to achieve high throughput on fpga platforms. Compared to previous works aiming at data rates beyond 100 Gbit/s, our design makes use of an alternative block cipher and an alternative mode of operation, namely Serpent and the offset codebook mode of operation, respectively. Using four cipher cores for the encryption part of the AE architecture, we achieve a throughput of 141 Gbit/s on an Altera Stratix IV fpga. The design requires 39 kALMs and runs at a maximum clock frequency of 275 MHz. This represents, to the best of our knowledge, the fastest full implementation of an AE scheme on fpgas to date. In order to make the design applicable in a real-world environment, we developed a custom-designed printed circuit board for the Stratix IV fpga, suitable to process data with up to 100 Gbit/s. © IFIP international Federation for Information Proessing 2013.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

Applications of crystalline indium-gallium-zinc-oxide technology to LSI: Memory, processor, image sensor, and field programmable gate array

Applications of crystalline indium-gallium-zinc-oxide techno...

引用

5th Asia symposium on Quality Electronic Design, ASQED 2013

作者： Kurokawa, Yoshiyuki Okamoto, Yuki Nakagawa, Takashi Aoki, Takeshi Ikeda, Masataka Kozuma, Munehiro Osada, Takeshi Ikeda, Takayuki Yamade, Naoto Okazaki, Yutaka Miyairi, Hidekazu Fujita, Masahiro Koyama, Jun Yamazaki, Shunpei Semiconductor Energy Laboratory Co. Ltd. 398 Hase Atsugi-shi Kanagawa Japan University of Tokyo 2-11-16 Yayoi Bunkyo-ku Tokyo Japan

ISBN: (纸本)9781479913145

Crystalline In-Ga-Zn Oxide (IGZO) including c-axis aligned crystal (CAAC) enables FETs to show high reliability and extremely low off-state current. CAAC-IGZO technology is expected to grow to main technology of next-generation displays and is already contributing to mass-production of liquid crystal displays. In this paper by focusing on a very important feature of CAAC-IGZO FET, extremely low off-state current, its pioneering various applications to LSI are reviewed and discussed. In particular, a success in development of a hybrid process of CMOS FETs and CAAC-IGZO FETs promotes our developments of novel memories, processors, image sensors, and recently, field programmable gate arrays (fpga). © 2013 IEEE.

关键词： Oxide semiconductors

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共81页 << < 21 22 23 24 25 26 27 28 29 30 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：