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检索条件"任意字段=2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013"

共 809 条记录，以下是251-260 订阅

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fpga-Based HPC Application Design for Non-Experts

FPGA-Based HPC Application Design for Non-Experts

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international symposium on Rapid System Prototyping / Embedded Systems Week

作者： Uliana, David Kepa, Krzysztof Athanas, Peter Virginia Polytech Inst & State Univ Blacksburg VA 24061 USA

ISBN: (纸本)9781479924097

In the current era of big-data computing, most non-engineer domain experts lack the skills needed to design fpga-based hardware accelerators to address big-data problems in their fields. This work presents bFlow, a development environment that facilitates the assembly of such accelerators, specifically those targeting fpga-based hybrid computing platforms, such as the Convey HC series. This framework attempts to address the above problem by making use of an abstracted, graphical front-end more friendly to users without computer engineering backgrounds than traditional, HDL-based design environments, as well as by accelerating bitstream compilation by means of incremental implementation techniques. bFlow's performance, usability, and application to big-data life-science problems were tested by participants of an NSF-funded Summer Institute organized by the Virginia Bioinformatics Institute (VBI). In about one week, a group of four non-engineering participants made significant improvements to a reference Smith-Waterman implementation, adding functionality and scaling theoretical throughput by a factor of 32.

关键词： field programmable gate arrays hardware description languages logic design

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Live Demonstration: Real-Time Audio Restoration using Sparse Signal Recovery

Live Demonstration: Real-Time Audio Restoration using Sparse...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： Bellasi, D. Maechler, P. Burg, A. Felber, N. Kaeslin, H. Studer, C. Swiss Fed Inst Technol Zurich Switzerland Ecole Polytech Fed Lausanne Lausanne Switzerland Rice Univ Houston TX USA

ISBN: (纸本)9781467357623;9781467357609

We demonstrate the restoration of audio signals corrupted by clicks and pops using techniques from sparse signal recovery and compressive sensing. The demonstration features real-time signal restoration using the approximate message passing algorithm on an fpga prototyping board. To highlight the restoration performance of our implementation, we remove clicks and pops from old phonograph recordings in real time.

关键词： approximation theory audio signal processing field programmable gate arrays signal reconstruction signal restoration

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Design of LUT based RNS Reverse Converters

Design of LUT based RNS Reverse Converters

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IEEE 17th international symposium on Consumer Electronics (ISCE)

作者： Kong, Wei Lam Vun, Nicholas Chan Hua Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore

ISBN: (纸本)9781467361996

This paper presents the strategies to implement Residue Number System reverse converter based on the Look-Up Table (LUT) approach that is applicable for general moduli set. The approach makes use of partitioning to divide the LUT entries into multiple small LUTs in parallel, where their outputs can be further selected to obtain the equivalent binary number. Pipelining architecture is also incorporated to improve the operation speed. These techniques are hence suitable for general moduli set with large moduli value. Implementation results based on fpga further demonstrate the feasibility and effectiveness of the proposed approach.

关键词： field programmable gate arrays pipeline processing residue number systems table lookup

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fpga Based Extension to the Multichannel Pixel Readout ASIC

FPGA Based Extension to the Multichannel Pixel Readout ASIC

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60th IEEE Nuclear Science symposium (NSS) / Medical Imaging Conference (MIC) / 20th international Workshop on Room-Temperature Semiconductor X-ray and Gamma-ray Detectors

作者： Maj, Piotr AGH Univ Sci & Technol Fac Elect Engn Automat Comp Sci & Biomed Engn Dept Measurement & Elect PL-30059 Krakow Poland

ISBN: (纸本)9781479905348

This paper presents the realization of the fpga extension to the multichannel, pixel readout ASIC called VIPIC, designed in the collaboration between Fermi National Laboratory and AGH UST for X-ray Photon Correlation Spectroscopy (XPCS) experiments at BNL (Brookhaven National Laboratory). The fpga was proposed to extend the digital backend of the chip and supply it with 32-bit long counters allowing effective operation in imaging mode, working in continuous readout mode at 50 MHz together with intelligent control of supporting digital lines, communication verification, the data compression and providing higher abstraction level for other systems communicating with it. The paper presents a new approach of building such systems including tools and methods allowing implementation of high-speed data processing without deep knowledge of fpga structure or Hardware Description Language (HDL) experience. The advantage of LabVIEW (TM) graphical system design for both fpga and Real-Time OS programming is presented for building testing setup including automatic procedures like threshold scans and automatic correction with user-defined algorithms.

关键词： field programmable gate arrays (fpga)

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Power supply glitch induced faults on fpga: an in-depth analysis of the injection mechanism

Power supply glitch induced faults on FPGA: an in-depth anal...

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IEEE 19th international On-Line Testing symposium (IOLTS)

作者： Zussa, Loic Dutertre, Jean-Max Clediere, Jessy Tria, Assia Ecole Natl Super Mines F-13120 Gardanne France CEA LETI F-13120 Gardanne France

ISBN: (纸本)9781479906642

Secure circuits are prone to a wide range of physical attacks. Among those are fault attacks based on modifying the circuit environment in order to change its behaviour or to induce faults into its computations. There are many common means used to inject such faults: laser shots, electromagnetic pulses, overclocking, chip underpowering, temperature increase, etc. In this paper we study the effect of negative power supply glitches on a fpga. The obtained faults were compared to faults injected by clock glitches. As a result, both power and clock glitch induced faults were found to be identical. Because clock glitches are related to timing constraint violations, we shall consider that both power and clock glitches share this common fault injection mechanism. We also further studied the properties of this fault injection means.

关键词： clocks cryptography fault tolerant computing field programmable gate arrays timing circuits

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An fpga router for alternative reconfiguration flows

An FPGA router for alternative reconfiguration flows

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2013 IEEE 37th Annual Computer Software and Applications Conference, COMPSAC 2013

作者： Zha, Wenwei Athanas, Peter Bradley Department of Electrical and Computer Engineering Virginia Polytechnic Institute State University Blacksburg VA 24060 United States

ISBN: (纸本)9780769549798

An fpga router is developed using both the PathFinder and A* algorithms. Instead of the popular routing channel and rack model that is widely adopted by the research community, a modified routing model based on the architecture description for Xilinx devices (XDLRC) is applied. As a result, the proposed router works for any real device with an XDLRC description, which makes it a good candidate for fpga reconfiguration flows. Tests of routing MCNC benchmark circuits are run for five different fpga devices. The performance results are comparable to those of VPR and ROCR. Two useful application of the proposed router are demonstrated. One is fast module assembly, which runs tens of times faster than the vendor tool. The other is routing-free sandbox creation which outperforms OpenPR in terms of run time. © 2013 IEEE.

关键词： field programmable gate arrays (fpga)

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Model of video encryption based on fpga

引用

2013 3rd international symposium on Chemical Engineering and Material Properties, ISCEMP 2013

作者： Zhao, Jin Hui Wang, Xiao Hong Department of Computer Science and Technology Communication University of China Beijing 100024 China

ISBN: (纸本)9783037858363

On the Internet, most of media information is transmitted in plaintext. Some others can easily tamper or intercut the information, so there are threats to those information transmitted in plaintext. This paper designs a model of video encryption which uses AES algorithm and the model is based on fpga platform. The model does the encryption in paralleling on XUPV5-110T development board. The encryption model can ensure the security and integrity of media information during the transmission process between a certain links on the network. © (2013) Trans Tech Publications, Switzerland.

关键词： field programmable gate arrays (fpga)

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A CAM-based Information Detection Hardware System for fast exact pattern matching

A CAM-based Information Detection Hardware System for fast e...

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2013 IEEE 56th international Midwest symposium on Circuits and Systems, MWSCAS 2013

作者： Le, Duc-Hung Cao, Tran-Bao-Thuong Inoue, Katsumi Pham, Cong-Kha University of Electro-Communications Tokyo Japan University of Science Ho Chi Minh City Viet Nam Advanced Original Technologies Chiba Japan

ISBN: (纸本)9781479900664

A CAM-based Information Detection Hardware System for fast exact pattern matching is implemented on a hardware system with fpga and ASIC. The system has a simple structure, does not employ any Central Processor Unit (CPU) as well as complicated algorithms. We take advantage of Content Addressable Memory (CAM) which has an ability of parallel multi-match mode for designing the system. The system is applied to fast pattern matching with various required search patterns without using any search principles. In this paper, the authors present the system for exact pattern matching on 2-D data. © 2013 IEEE.

关键词： field programmable gate arrays (fpga)

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Color-Space Image Compression with Hardware Self-Organizing Map

Color-Space Image Compression with Hardware Self-Organizing ...

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international symposium on Intelligent Signal Processing and Communications Systems (ISPACS)

作者： Terahara, Naoki Oba, Yoshiro Hikawa, Hiroomi Kansai Univ Grad Sch Sci & Engn Suita Osaka 5648680 Japan Mitsubishi Elect Micro Comp Applicat Software Co Amagasaki Hyogo Japan

ISBN: (纸本)9781467363617;978146736360+0

This paper discusses the use of Self-organizing map (SOM) for color-space image compression. Two types of compressions, i.e., color and space compressions, are carried out by SOM. The feasibility of the proposed compression method is verified by computer simulation. By applying both color and space compression, higher compression is achieved. In addition, the proposed compression system is implemented in hardware using a hardware SOM. The system is designed by using VHDL, and operation of the system is verified by fpga implementation. Experimental result shows that the maximum clock frequency of this system is 26 MHz, and a single image is compressed with 25.2 ms, which yields 39.7 fps.

关键词： data compression field programmable gate arrays image coding image colour analysis self-organising feature maps

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Design and Implementation of a 16-Bit Flexible ROM-less Direct Digital Synthesizer

Design and Implementation of a 16-Bit Flexible ROM-less Dire...

引用

IEEE 56th international Midwest symposium on Circuits and Systems (MWSCAS)

作者： Dommaraju, Sunny Raj Ren, Saiyu Lee, George Y. Wright State Univ Dept Elect Engn Dayton OH 45435 USA

ISBN: (纸本)9781479900664

A ROM-less direct digital synthesizer architecture is presented in this paper. This architecture eliminates the ROM-based phase to sine wave amplitude converter, which is a bottleneck for pushing clock frequencies into the gigahertz range. The design consists of a 16-bit phase accumulator, a set of 18 band pass finite impulse response filters, a 12-bit digital to analog converter and a low pass filter to produce a sine wave with output frequencies ranging from 36 MHz to 72 MHz with a resolution of 3.05 KHz and a 55 dB spur free dynamic range. The same hardware can be used to achieve output frequency ranging from hertz to gigahertz and a 191 Hz resolution by changing the clock frequency. A resolution of 0.05 Hz can be achieved by using a 32-bit phase accumulator. This design was simulated in Xilinx system generator (Sysgen) and mapped on to Virtex-6 fpga. The analysis results of the Sysgen and fpga data show that the proposed design is an effective alternative.

关键词： field programmable gate arrays (fpga)

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