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检索条件"任意字段=2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013"

共 809 条记录，以下是21-30 订阅

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FlightLLM: Efficient Large Language Model Inference with a Complete Mapping Flow on fpgas 24

FlightLLM: Efficient Large Language Model Inference with a C...

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32nd acm international symposium on field-programmable gate arrays, fpga 2024

作者： Zeng, Shulin Liu, Jun Dai, Guohao Yang, Xinhao Fu, Tianyu Wang, Hongyi Ma, Wenheng Sun, Hanbo Li, Shiyao Huang, Zixiao Dai, Yadong Li, Jintao Wang, Zehao Zhang, Ruoyu Wen, Kairui Ning, Xuefei Wang, Yu Tsinghua University Infinigence-AI China Shanghai Jiao Tong University Infinigence-AI China Tsinghua University China Infinigence-AI

ISBN: (纸本)9798400704185

Transformer-based Large Language Models (LLMs) have made a significant impact on various domains. However, LLMs' efficiency suffers from both heavy computation and memory overheads. Compression techniques like sparsification and quantization are commonly used to mitigate the gap between LLM's computation/memory overheads and hardware capacity. However, existing GPU and transformer-based accelerators cannot efficiently process compressed LLMs, due to the following unresolved challenges: low computational efficiency, underutilized memory bandwidth, and large compilation overheads. This paper proposes FlightLLM, enabling efficient LLMs inference with a complete mapping flow on fpgas. In FlightLLM, we highlight an innovative solution that the computation and memory overhead of LLMs can be solved by utilizing fpga-specific resources (e.g., DSP48 and heterogeneous memory hierarchy). We propose a configurable sparse DSP chain to support different sparsity patterns with high computation efficiency. Second, we propose an always-on-chip decode scheme to boost memory bandwidth with mixed-precision support. Finally, to make FlightLLM available for real-world LLMs, we propose a length adaptive compilation method to reduce the compilation overhead. Implemented on the Xilinx Alveo U280 fpga, FlightLLM achieves 6.0× higher energy efficiency and 1.8× better cost efficiency against commercial GPUs (e.g., NVIDIA V100S) on modern LLMs (e.g., LLaMA2-7B) using vLLM and SmoothQuant under the batch size of one. FlightLLM beats NVIDIA A100 GPU with 1.2× higher throughput using the latest Versal VHK158 fpga. © 2024 Owner/Author.

关键词： field programmable gate arrays (fpga)

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HiSpMV: Hybrid Row Distribution and Vector Buffering for Imbalanced SpMV Acceleration on fpgas 24

HiSpMV: Hybrid Row Distribution and Vector Buffering for Imb...

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32nd acm international symposium on field-programmable gate arrays, fpga 2024

作者： Rajashekar, Manoj B. Tian, Xingyu Fang, Zhenman Simon Fraser University BurnabyBC Canada

ISBN: (纸本)9798400704185

Sparse matrix-vector multiplication (SpMV) is a fundamental operation in numerous applications such as scientific computing, machine learning, and graph analytics. While recent studies have made great progress in accelerating SpMV on HBM-equipped fpgas, there are still multiple remaining challenges to efficiently accelerate imbalanced SpMV where the distribution of non-zeros in the sparse matrix is imbalanced across different rows. First, the imbalanced workload distribution among the parallel processing elements (PEs) leads to PE under-utilization and performance degradation. Second, the read-after-write dependency of the long-latency floating-point accumulation on the output vector causes pipeline stalls inside the PE, and existing scheduling solutions for balanced matrices no longer work effectively for imbalanced ones. Third, the memory access latency for the often overlooked input vector becomes a new performance bottleneck after the SpMV acceleration. To address the above challenges, in this work, we propose HiSpMV to accelerate imbalanced SpMV on HBM-equipped fpgas. First, we design a hybrid row distribution network to enable both inter-row and intra-row distribution to achieve more balance. Second, we implement fully pipelined floating-point accumulation on the output vector using a combination of an adder tree and circular buffer. Third, we design a hybrid buffering technique to optimize the input vector loading from off-chip memory by dynamically switching between private partitioned buffers and shared ping-pong buffers. Lastly, we also developed an automation framework to automatically generate the optimized HiSpMV accelerator based on the user configurations. Experimental results demonstrate that HiSpMV achieves a geomean speedup of 13.7x (up to 60x) for highly imbalanced matrices, compared to state-of-the-art SpMV accelerator Serpens on the AMD-Xilinx Alveo U280 HBM-based fpga. Compared to Intel MKL running on a 24-core Xeon Silver 4214 CPU, HiSpMV achi

关键词： field programmable gate arrays (fpga)

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Multi-input Serial Adders for fpga-like Computational Fabric 22

Multi-input Serial Adders for FPGA-like Computational Fabric

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2022 acm/sigda international symposium on field-programmable gate arrays, fpga 2022

作者： Schmit, Herman Denton, Matthew Google Research Mountain ViewCA United States

ISBN: (纸本)9781450391498

In this paper, we present a new functional unit to replace the LUT in an fpga-like computational fabric designed specifically for use to accelerate instance-specific sparse integer matrix multiplication. We use a suite of matrices, the VPR place-and-route tool, and modern architecture representations of the interconnect to examine this architectural idea. The new cell, called the K - ADD, increases density by 2.5× to 4×, and increases performance by 8% to 30% by simultaneously increasing the clock rate and reducing the number of cycles to compute the product. This benefit magnifies the two-orders-of-magnitude advantage of using instance-specific matrix multipliers demonstrated in prior work. We investigate the cluster size, N, across multiple technology nodes. In that investigation, we see a sustained benefit to a larger cluster size (N=8). This observation holds for both netlists mapped to a 6 - LUT and to a 6 - ADD, which implies this behavior has more to do with the peculiar structure of these matrix multiplication netlists, not the different functional unit. © 2022 acm.

关键词： field programmable gate arrays (fpga)

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Towards Agile DNN Accelerator Design Using Incremental Synthesis on fpgas 22

Towards Agile DNN Accelerator Design Using Incremental Synth...

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2022 acm/sigda international symposium on field-programmable gate arrays, fpga 2022

作者： Xiao, Qingcheng Liang, Yun Peking University Beijing China

ISBN: (纸本)9781450391498

Hardware-software co-design is the new trend for deep neural network and fpga accelerator development, which iteratively revises and tunes the full system. The bottleneck of the approach lies in the time-consuming hardware synthesis. In this paper, we propose an incremental synthesis framework Acoda to rapidly design DNN accelerators on fpgas. Based on the observation that most revisions to DNNs are minor and local, Acoda reuses existing hardware modules and incrementally modifies the accelerator. It first detects the software revisions using a graph edit distance algorithm. Then, it maps the software revisions to hardware revisions through a multi-level reuse hierarchy. As a result, Acoda speeds up the design process by 9.31X to 34.17X and achieves performance results comparable to off-the-shelf accelerators. © 2022 acm.

关键词： field programmable gate arrays (fpga)

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Accounting for Floorplan Irregularity and Configuration Dependence in fpga Routing Delay Models 24

Accounting for Floorplan Irregularity and Configuration Depe...

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24th international symposium on Quality Electronic Design (ISQED)

作者： Barajas, Gabriel Greene, Jonathan W. Li, Fei Tandon, James Microchip San Jose CA 95134 USA Cambios Comp LLC Palo Alto CA USA Calif State Univ East Bay Hayward CA USA

ISBN: (纸本)9798350334753

Accurate delay estimates for a user application implemented in a field-programmable gate Array (fpga) are essential for a quality fpga timing flow and to avoid leaving performance on the table. fpga inter-cluster routing consists of wire segments of a limited number of types which repeat in a somewhat regular pattern, interconnected by configurable muxes. The delay at any fanout of a segment can be significantly impacted by configuration-dependent capacitive loading related to other fanouts. Also, the insertion of RAM and math blocks into the fpga floorplan introduces irregular stretching of the wire segments, altering their delays. We explain why and how commercial fpga software typically employs a parameterized model for the delay at each fanout of a segment, based on the configuration and the irregularities present, with the parameters determined by fitting SPICE simulation data for a representative sample of cases. We propose incorporating readily-computed common path resistance values into the model. This enables high accuracy with fewer parameters and without the large amounts of SPICE data that would otherwise be required to explore interactions between floorplan irregularities and the set of active fanouts. In combination with other features of our models, errors in segment delay are reduced by almost half.

关键词： field-programmable gate arrays fpgas delay estimation Elmore delay common path resistance

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Quality-driven Design Methodology for PUFs in fpgas for Secure IoT 24

Quality-driven Design Methodology for PUFs in FPGAs for Secu...

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24th international symposium on Quality Electronic Design (ISQED)

作者： Wang, Xiangyun Song, Yicheng Prakash, Katyayani Zilic, Zeljko Langsetmo, Tomas McGill Univ Montreal PQ Canada KNOX Ind Inc Montreal PQ Canada

ISBN: (纸本)9798350334753

The emergence of Internet of Things (IoT) has placed strong emphasis on security. Physical Unclonable Functions (PUFs) are a promising low-cost security solution for IoT. Since field-programmable gate arrays (fpgas) are more trusted than custom Integrated Circuits (ICs) in building secure systems, implementing PUFs in fpgas is appealing. In this paper, we propose a methodology for improving the quality of delay-based PUFs on fpgas. With our method, an asymmetric delay-based PUF has been predictably designed for temperature- and aging-independent operation. Furthermore, the resistance to modeling attacks is built into the design.

关键词： Physical Unclonable Function (PUF) Internet-of-Things (IoT) field-programmable gate Array (fpga) Hardware Security Design Methodology

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How to shrink my fpgas - Optimizing Tile Interfaces and the Configuration Logic in FABulous fpga Fabrics 22

How to shrink my FPGAs - Optimizing Tile Interfaces and the ...

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2022 acm/sigda international symposium on field-programmable gate arrays, fpga 2022

作者： Chung, King Lok Dao, Nguyen Yu, Jing Koch, Dirk Computer Science University of Manchester Manchester United Kingdom

ISBN: (纸本)9781450391498

Commercial fpgas from major vendors are extensively optimized, and fabrics use many hand-crafted custom cells, including switch matrix multiplexers and configuration memory cells. The physical design optimizations commonly improve area, latency (=speed), and power consumption together. This paper is dedicated to improving the physical implementation of fpga tiles and the configuration storage in SRAM fpgas. This paper proposes to remap configuration bits and interface wires to implement tightly packed tiles. Using the FABulous fpga framework, we show that our optimizations are virtually for free but can save over 20% in area and improve latency at the same time. We will evaluate our approach in different scenarios by changing the available metal layers or the requested channel capacity. Our optimizations consider all tiles and we propose a flow that resolves dependencies between the CLBs and other tiles. Moreover, we will show that frame-based reconfiguration is, in almost all cases, better than shift register configuration. © 2022 acm.

关键词： field programmable gate arrays (fpga)

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An fpga-based RNN-T inference accelerator with PIM-HBM 22

An FPGA-based RNN-T inference accelerator with PIM-HBM

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2022 acm/sigda international symposium on field-programmable gate arrays, fpga 2022

作者： Kang, Shin-Haeng Lee, Sukhan Kim, Byeongho Kim, Hweesoo Sohn, Kyomin Kim, Nam Sung Lee, Eojin Samsung Electronics Hwaseong Korea Republic of Seoul National University Seoul Korea Republic of Inha University Incheon Korea Republic of

ISBN: (纸本)9781450391498

In this paper, we implemented a world-first RNN-T inference accelerator using fpga with PIM-HBM that can multiply the internal bandwidth of the memory. The accelerator offloads matrix-vector multiplication (GEMV) operations of LSTM layers in RNN-T into PIM-HBM, and PIM-HBM reduces the execution time of GEMV significantly by exploiting HBM internal bandwidth. To ensure that the memory commands are issued in a pre-defined order, which is one of the most important constraints in exploiting PIM-HBM, we implement a direct memory access (DMA) module and change configuration of the on-chip memory controller by utilizing the flexibility and reconfigurability of the fpga. In addition, we design the other hardware modules for acceleration such as non-linear functions (i.e., sigmoid and hyperbolic tangent), element-wise operation, and ReLU module, to operate these compute-bound RNN-T operations on fpga. For this, we prepare FP16 quantized weight and MLPerf input datasets, and modify the PCIe device driver and C++ based control codes. On our evaluation, our accelerator with PIM-HBM reduces the execution time of RNN-T by 2.5 × on average with 11.09% reduced LUT size and improves energy efficiency up to 2.6 × compared to the baseline. © 2022 acm.

关键词： field programmable gate arrays (fpga)

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Online Training from Streaming Data with Concept Drift on fpgas 24

Online Training from Streaming Data with Concept Drift on FP...

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24th international symposium on Quality Electronic Design (ISQED)

作者： Roorda, Esther Wilton, Steven J. E. Univ British Columbia Vancouver BC Canada

ISBN: (纸本)9798350334753

In dynamic environments, the inputs to machine learning models may exhibit statistical changes over time, through what is called concept drift. Incremental training can allow machine learning models to adapt to changing conditions and maintain high accuracy by continuously updating network parameters. In the context of fpga-based accelerators however, online incremental learning is challenging due to resource and communication constraints, as well as the absence of labelled training data. These challenges have not been fully evaluated or addressed in existing research. In this paper, we present and evaluate strategies for performing incremental training on streaming data with concept drift on fpga-based platforms. We first present fpga-based implementations of existing training algorithms to demonstrate the viability of online training with concept shift and to evaluate design tradeoffs. We then propose a technique for online training without labelled data and demonstrate its potential in the context of fpga-based hardware acceleration.

关键词： field programmable gate arrays (fpga)

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RapidStream: Parallel Physical Implementation of fpga HLS Designs 22

RapidStream: Parallel Physical Implementation of FPGA HLS De...

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2022 acm/sigda international symposium on field-programmable gate arrays, fpga 2022

作者： Guo, Licheng Maidee, Pongstorn Zhou, Yun Lavin, Chris Wang, Jie Chi, Yuze Qiao, Weikang Kaviani, Alireza Zhang, Zhiru Cong, Jason University of California Los Angeles Los AngelesCA United States Xilinx Inc. San JoseCA United States Ghent University Ghent Belgium Cornell University IthacaMI United States

ISBN: (纸本)9781450391498

fpgas require a much longer compilation cycle than conventional computing platforms like CPUs. In this paper, we shorten the overall compilation time by co-optimizing the HLS compilation (C-to-RTL) and the back-end physical implementation (RTL-to-bitstream). We propose a split compilation approach based on the pipelining flexibility at the HLS level, which allows us to partition designs for parallel placement and routing then stitch the separate partitions together. We outline a number of technical challenges and address them by breaking the conventional boundaries between different stages of the traditional fpga tool flow and reorganizing them to achieve a fast end-to-end compilation. Our research produces RapidStream, a parallelized and physical-integrated compilation framework that takes in an HLS dataflow program in C/C++ and generates a fully placed and routed implementation. When tested on the Xilinx U250 fpga with a set of realistic HLS designs, RapidStream achieves a 5-7X reduction in compile time and up to 1.3X increase in frequency when compared to a commercial-off-the-shelf toolchain. In addition, we provide preliminary results using a customized open-source router to reduce the compile time up to an order of magnitude in the cases with lower performance requirements. © 2022 acm.

关键词： field programmable gate arrays (fpga)

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