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检索条件"任意字段=2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013"

共 809 条记录，以下是291-300 订阅

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Fault Tolerant CAN Bus Control System Implemented into fpga

Fault Tolerant CAN Bus Control System Implemented into FPGA

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IEEE 16th international symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)

作者： Szurman, Karel Kastil, Jan Straka, Martin Kotasek, Zdenek UNIS As Jundrovska 33 Brno 62400 Czech Republic Brno Univ Technol CZ-61266 Brno Czech Republic

ISBN: (纸本)9781467361361;9781467361354

For various types of applications, it is necessary to guarantee maximal level of fault tolerance and high reliability of components, avionic and railway applications can serve as an example of these applications. In these devices, electronic components are exhibited to the environment conditions, from among them especially cosmic radiation can have an undesired and destructive effect. In this paper, the basic ideas of the design and implementation of CAN bus based control system into fpga platform is described. The bus control system uses CANAerospace application protocol. The fault tolerance features of the developed system are improved by TMR architecture. Then, experiments with SEU injection into the fpga configuration memory with both non-TMR and TMR architectures are described, the results presented and evaluated. In these experiments, SEU injection framework developed during our previous research was used which injects SEU failures into running fpga design.

关键词： Fault tolerance field programmable gate arrays Single event upsets NUCLEOPORIN, 214-KD calcium ammonium nitrate Motor buses RAILWAY APPLICATION Cosmic radiation tunneling magnetoresistance control systems

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An fpga based cut-through switch optimized for one-step PTP and real-time Ethernet

An FPGA based cut-through switch optimized for one-step PTP ...

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2013 7th international IEEE symposium on Precision Clock Synchronization for Measurement, Control and Communication, ISPCS 2013

作者： Flatt, Holger Jasperneite, Jürgen Schewe, Frank Fraunhofer IOSB-INA Application Center Industrial Automation Langenbruch 6 32657 Lemgo Germany Phoenix Contact Electronics GmbH Business Unit I/O and Networks Development Network Technology Dringenauer Straße 30 31812 Bad Pyrmont Germany

ISBN: (纸本)9781479902415

This paper presents an fpga based Ethernet cutthrough switch that is optimized for one-step PTP clock synchronization and fast forwarding of real-time Ethernet frames. Whereas a standard switch ASIC provides sophisticated mechanisms for switching of non-real-time frames, an attached fpga implements cut-through switching of real-time frames and synchronization events. Moreover, timestamping of synchronization events, one-step bridge delay compensation, peer-delay responses for power profile and a servo clock are implemented in hardware. The results show that even a low-cost Xilinx Spartan 6 fpga comprising 47,000 Look-up tables can fulfill the requirements for switching 6 Ethernet ports at 100 Mbps. The combination of cut-through forwarding and transparent one-step clock synchronization yields to bridge delays less than 3 microseconds for both real-time Ethernet data and synchronization events. Therefore, the presented switch can be flexibly integrated into time-synchronized real-time networks in order to provide improved switching functions. © 2013 IEEE.

关键词： field programmable gate arrays (fpga)

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Reconfigurable multi-core architecture - A plausible solution to the von Neumann performance bottleneck

Reconfigurable multi-core architecture - A plausible solutio...

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2013 IEEE 7th international symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013

作者： Lu, Chun-Hsien Lin, Chih-Sheng Chao, Hung-Lin Shen, Jih-Sheng Hsiung, Pao-Ann Department of Computer Science and Information Engineering National Chung Cheng University Chiayi Taiwan-621 Taiwan

ISBN: (纸本)9780768550862

The ill-famed von Neumann bottleneck has been the main performance hurdle since the invention of computers. Although several techniques such as separate data/instruction caches, branch prediction, and parallel computing have been proposed and improved efficiency, the throughput bottleneck between CPU and memory is still very much there. We propose a novel reconfigurable multi-core architecture (RMA) to address this issue via the dynamic allocation of heterogeneous computing resources and distributed memory. We show how this is feasible with the state-of-the-art technologies of dynamic partial reconfiguration of hardware resources and runtime operating system configuration. Experiments and analysis show how RMA alleviates the performance bottleneck. © 2013 IEEE.

关键词： field programmable gate arrays (fpga)

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Digital current loop for permanent magnet linear synchronous motor based on DSP and fpga

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9th international symposium on Linear Drives for Industry Applications, LDIA 2013

作者： Zhang, Yong Zhang, Xin Min Lu, Qin Fen Chen, Yi Ye, Yun Yue College of Electrical Engineering Zhejiang University China

ISBN: (纸本)9783037858639

In the high-precision servo control system of permanent magnet linear synchronous motor (PMLSM), the regulation of current loop has a direct effect on the control performances such as accuracy, response speed etc. In order to improve the control performances, a digital current loop control scheme based on DSP and fpga is presented in this paper. fpga is used to collect data, while DSP is for completing parallel collection of the input signals read and written from fpga. P control, P uniting feed-forward compensation control and variable proportional gain control are investigated. Since the method of variable proportional gain can easily meet the requirement of current static error and quick response under different frequencies, PI control can basically eliminate the static error. With rotor initial positioning method, the current closed-loop control is proposed and compared with current open-loop control. © (2013) Trans Tech Publications, Switzerland.

关键词： field programmable gate arrays (fpga)

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Approximate Matrix Inversion for High-Throughput Data Detection in the Large-Scale MIMO Uplink

Approximate Matrix Inversion for High-Throughput Data Detect...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： Wu, Michael Yin, Bei Vosoughi, Aida Studer, Christoph Cavallaro, Joseph R. Dick, Chris Rice Univ Houston TX 77251 USA Xilinx San Jose CA USA

ISBN: (纸本)9781467357623;9781467357609

The high processing complexity of data detection in the large-scale multiple-input multiple-output (MIMO) uplink necessitates high-throughput VLSI implementations. In this paper, we propose-to the best of our knowledge-first matrix inversion implementation suitable for data detection in systems having hundreds of antennas at the base station (BS). The underlying idea is to carry out an approximate matrix inversion using a small number of Neumann-series terms, which allows one to achieve near-optimal performance at low complexity. We propose a novel VLSI architecture to efficiently compute the approximate inverse using a systolic array and show reference fpga implementation results for various system configurations. For a system where 128 BS antennas receive data from 8 single-antenna users, a single instance of our design processes 1.9Mmatrices/s on a Xilinx Virtex-7 fpga, while using only 3.9% of the available slices and 3.6% of the available DSP48 units.

关键词： MIMO communication VLSI antennas approximation theory communication complexity field programmable gate arrays matrix inversion radio links

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Hardware acceleration of TEA and XTEA algorithms on fpga, GPU and multi-core processors (abstract only) 13

Hardware acceleration of TEA and XTEA algorithms on FPGA, GP...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Vivek Venugopal Devu Manikantan Shila United Technologies Research Center E Hartford CT USA

ISBN: (纸本)9781450318877

field programmable gate arrays (fpga) are extensively used for rapid prototyping in embedded system applications. While hardware acceleration can be done via specialized processors like a Graphical Processing Unit (GPU), they can also be accomplished with fpgas for more specialized scenarios. GPUs essentially consist of massively parallel cores and have high memory bandwidth; fpgas, on the other hand, provide flexibility in terms of customizable I/O and computational resources. In this paper, we explore the usage of GPUs and fpgas as cryptographic co-processors in streaming dataflow systems with huge rate of data inhalation. Two classic lightweight encryption algorithms, Tiny Encryption Algorithm (TEA) and Extended Tiny Encryption Algorithm (XTEA), are targeted for implementation on GPUs and fpgas. The GPU implementations of TEA and XTEA in this study depict a maximum speedup of 13x over CPU based implementation. The pipelined fpga implementation is able to realize a throughput of 6-9x more than the GPU for small plaintext sizes.

关键词： cryptography graphics processing units tiny encryption algorithm field programmable gate arrays parallel processing

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Architecture exploration of high-performance floating-point fused multiply-Add units and their automatic use in high-level synthesis

Architecture exploration of high-performance floating-point ...

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2013 IEEE 37th Annual Computer Software and Applications Conference, COMPSAC 2013

作者： Liebig, Bjorn Huthmann, Jens Koch, Andreas Technische Universiẗat Darmstadt Embedded Systems and Applications Group Darmstadt Germany

ISBN: (纸本)9780769549798

Multiply-Add operations form a crucial part of many digital signal processing and control engineering applications. Since their performance is crucial for the application-level speed-up, it is worthwhile to explore a wide spectrum of implementations alternatives, trading increased area/energy usage to speed-up units on the critical path of the computation. This paper examines existing solutions and proposes two new architectures for floating-point fused multiply-Adds, and also considers the impact of different in-fabric features of recent fpga architectures. The units rely on different degrees of carry-save arithmetic improve performance by up to 2.5x over the closest state-of-The-Art competitor. They are evaluated at the application level by modifying an existing high-level synthesis system to automatically insert the new units for computations on the critical path of three different convex solvers. © 2013 IEEE.

关键词： field programmable gate arrays (fpga)

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The Status of High-Speed Trigger Multiplexer Module with Aurora Protocol Implemented on Arria II fpga for the Belle II Cylindrical Drift Chamber Detector

The Status of High-Speed Trigger Multiplexer Module with Aur...

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60th IEEE Nuclear Science symposium (NSS) / Medical Imaging Conference (MIC) / 20th international Workshop on Room-Temperature Semiconductor X-ray and Gamma-ray Detectors

作者： Teng, Y. -S. Wang, C. -H. Liu, S. -M. Shiu, J. -G. Lai, Y. -T. Lin, C. -S. Natl United Univ Dept Elect Engn Miaoli 36003 Taiwan

ISBN: (纸本)9781479905348

Based on the first prototype, a newly modified trigger multiplexer module (merger) is under development for the Central Drift Chamber (CDC) detector which will be used in the future Belle II experiment. The features of modified merger circuit board include two Arria II fpgas, four 3.125G optical modules and one 6.25G optical module for data transmission. The modified circuit board of merger was made and the data-link testing with Aurora protocol between the merger and the main trigger system (UT3) has been performed. Simple data reduction scheme within mergers and the schedule of the production plan will also be included here.

关键词： field programmable gate arrays (fpga)

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A low power all-digital self-calibrated temperature sensor using 65nm fpgas

A low power all-digital self-calibrated temperature sensor u...

引用

2013 IEEE international symposium on Circuits and Systems, ISCAS 2013

作者： Xie, Shuang Ng, Wai Tung Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto 10 King's College Road Toronto ON M5S 3G4 Canada

ISBN: (纸本)9781467357609

This paper presents an all-digital self-calibrated delay-line based temperature sensor. A continuous self-calibration technique is proposed to remove process variations and to generate direct digital representations of temperature. A power saving scheme using a hybrid counter/pulse position decoder is also introduced without any increase in area overhead. Four different architectures including traditional long and short delay-lines, and the proposed power saving hybrid sensor with long and short delay-lines are implemented on multiple 65nm Cyclone III fpgas along with an on-chip continuous self-calibration circuit. The logic utilization for a single sensor is as small as 60 Logic Elements (LE) and its measured power consumption is as low as 2.9 μW, with errors less than ±1.6 °C from 20 °C to 75 °C. © 2013 IEEE.

关键词： field programmable gate arrays (fpga)

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fpga-based HPC application design for non-experts (abstract only) 13

FPGA-based HPC application design for non-experts (abstract ...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： David Uliana Krzysztof Kepa Peter Athanas Virginia Tech Blacksburg VA USA

ISBN: (纸本)9781450318877

This paper presents bFlow, an fpga development framework for the rapid prototyping and implementation of hardware accelerators for hybrid computing platforms. This framework makes use of an abstracted, graphical front-end usable by those without computer engineering backgrounds, as well as an accelerated back-end that speeds up compilation times, increasing turns-per-day. bFlow's performance, usability, and application to the acceleration of big-data life-science problems verified by participants of the NSF-funded Summer Institute organised by the Virginia Bioinformatics Institute (VBI). In less than two weeks, a group of four non-computer science/computer engineering participants made modifications to a reference Smith-Waterman implementation, adding functionality and scaling throughput by a factor of four to 600 million base pairs per second.

关键词： field-programmable gate arrays bioinformatics co-processor heterogeneous computing design productivity convey HC-1 big-data

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