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检索条件"任意字段=2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013"

共 809 条记录，以下是301-310 订阅

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Wire-speed implementation of sliding-window aggregate operator over out-of-order data streams

Wire-speed implementation of sliding-window aggregate operat...

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2013 IEEE 7th international symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013

作者： Oge, Yasin Yoshimi, Masato Miyoshi, Takefumi Kawashima, Hideyuki Irie, Hidetsugu Yoshinaga, Tsutomu Graduate School of Information Systems University of Electro-Communications 1-5-1 Chofugaoka Chofu-shi Tokyo 182-8585 Japan E-Trees.Japan Inc. Daiwa Building 3F 2-9-2 Oowada-cho Hachioji Tokyo 192-0045 Japan University of Tsukuba 1-1-1 Tennodai Tsukuba Ibaraki 305-8577 Japan

ISBN: (纸本)9780768550862

This paper shows the design and evaluation of an fpga-based accelerator for sliding-window aggregation over data streams with out-of-order data arrival. We propose an order-agnostic hardware implementation technique for windowing operators based on a one-pass query evaluation strategy called Window-ID, which is originally proposed for software implementation. The proposed implementation succeeds to process out-of-order data items, or tuples, at wire speed due to the simultaneous evaluations of overlapping sliding-windows. In order to verify the effectiveness of the proposed approach, we have also implemented an experimental system as a case study. Our experiments demonstrate that the proposed accelerator with a network interface achieves an effective throughput around 760 Mbps or equivalently nearly 6 million tuples per second, by fully utilizing the available bandwidth of the network interface. © 2013 IEEE.

关键词： field programmable gate arrays (fpga)

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High-Performance Multiplierless Transform Architecture for HEVC

High-Performance Multiplierless Transform Architecture for H...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： Zhao, Wenjun Onoye, Takao Song, Tian Osaka Univ Sch Info Sci & Tech Dept Informat Syst Engn 1-1 Yamadaoka Suita Osaka 5650871 Japan Univ Tokushima Sch Engn Dept Elect & Elect Engn Yamashiro Tokushima 770 Japan

ISBN: (纸本)9781467357623;9781467357609

In this paper, a high- performance multiplierless VLSI architecture for the transform applied in the emerging video coding standard-High Efficiency Video Coding (HEVC) is presented. The proposed architecture can support a variety of transform sizes from 4x4 to 32x32, and some simplification strategies are adopted during the implementation, such as reusing part of a larger sized transform structure reused by smaller ones, and turning multiplications by constant into shift and sum operations. Synthesis results on the fpga platform indicate that the proposed design can double the throughput compared with previous work, with almost the same hardware cost. Moreover, synthesis results under 45nm technology show that it can support real- time processing of 4Kx2K (4096x2048, 30fps) video sequences. When a comparison index called "data throughput per unit area" is adopted, the proposed architecture is almost five times more efficient than is the previous design.

关键词： VLSI field programmable gate arrays video coding

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Human Respiratory Feature Extraction on An UWB Radar Signal Processing Platform

Human Respiratory Feature Extraction on An UWB Radar Signal ...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： Hsieh, Chi-Hsuan Shen, Yi-Hsiang Chiu, Yu-Fang Chu, Ta-Shun Huang, Yuan-Hao Natl Tsing Hua Univ Inst Commun Engn Hsinchu Taiwan Natl Tsing Hua Univ Dept Elect Engn Hsinchu Taiwan

ISBN: (纸本)9781467357623;9781467357609

This paper presents a human respiratory feature extraction algorithm and its implementation on an ultra-wideband (UWB) impulse-radio radar signal processing platform. The conventional human detection algorithms only extract the respiration rate by the radar system. However, there is more information that is never explored in the radar-detected respiratory signals. Thus, this study proposes a modified raised cosine waveform as the respiration model and an iterative feature extraction algorithm to acquire more respiratory features, such as inspiration and expiration speeds, respiration intensity, and respiration holding ratio. These extracted features can be regarded as the compressed signals for the long-term remote medical monitoring system. The proposed respiratory feature extraction algorithm is designed and implemented on a radar signal processing platform with an Radar front-end chip, an ARM processor, and an fpga chip. The proposed circuit can detect human respiratory signals from 0.1 to 1 Hz rate and analyze the respiratory features for each period of the respiratory signal.

关键词： feature extraction field programmable gate arrays iterative methods medical signal processing microprocessor chips radar detection radar signal processing ultra wideband radar

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Soft-IP Core Design of LVDS Receivers for Multichannel Ultrasound Imaging Applications

Soft-IP Core Design of LVDS Receivers for Multichannel Ultra...

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IEEE 17th international symposium on Consumer Electronics (ISCE)

作者： Tang, Song-Nien Lee, Chien-Ju Wu, Guo-Zua

ISBN: (纸本)9781467361996

In this paper, a soft IP core of LVDS (low-voltage differential signaling) receivers is proposed for multichannel ultrasound imaging systems or other applications. By careful cell-based design, a high-speed de-serializer is developed with control-able bit-shift and delay-adjustment operations. Moreover, using the proposed hybrid coarse-tune and two-level fine-tune schemes, a synchronization controller can perform efficient and robust multichannel LVDS signal synchronizing processes in cooperation with the de-serializer. The proposed LVDS IP core is synthesiz-able cell-based design, which is soft/portable to different circuit technology and system applications. Based on the proposed LVDS structure, four sets of 8-channel LVDS receivers were designed and implemented on a 32-channel fpga-based ultrasound imag-ing platform. Integrated with the ultrasound AFE/HVFE (analog and high-voltage front-end) module, a throughput of 480 Mb/s per channel can be achieved for test patterns, 32-channel ultrasound image and color-Doppler display.

关键词： field programmable gate arrays logic circuits microprocessor chips ultrasonic imaging

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Logic emulation with forced assertions: A methodology for rapid functional verification and debug

Logic emulation with forced assertions: A methodology for ra...

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5th Asia symposium on Quality Electronic Design, ASQED 2013

作者： Banerjee, Somnath Gupta, Tushar Gupta, Sanjay Mentor Graphics Pvt. Ltd. India

ISBN: (纸本)9781479913145

To improve debugging turnaround time of complex System-on-chip (SoC) designs on fpga based logic emulation systems, it is important to minimize the iterations through design recompilation or fpga reconfiguration process for validating repeated debugging changes. This paper presents a methodology for modeling debugging changes in terms of standalone assertion statements and evaluating their effect by running emulation without requiring any design modification or recompilation step, during emulation based debug. The set of assertions representing debugging changes are transformed into a set of constraints that are directly programmed into the emulator and an associated logic analyzer. When emulation is resumed from a bug-free state, these constraints are enforced by automatically forcing necessary signals to desired values, according to the specified assertions. Multiple debugging changes can thus be verified before eventually porting the fixes to design RTL followed by recompilation and emulation rerun. The proposed methodology also facilitates block based SoC development, by allowing a designer to enforce the correct functional behavior of some other block whose output affects the behavior of the block he is working on. Application of the proposed debugging system to debugging of real industry standard designs has been seen to reduce debugging turn-around time significantly. © 2013 IEEE.

关键词： field programmable gate arrays (fpga)

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HERA project's holistic evolutionary framework

HERA project's holistic evolutionary framework

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2013 IEEE 37th Annual Computer Software and Applications Conference, COMPSAC 2013

作者： Bartolini, Davide B. Carminati, Matteo Cancare, Fabio Santambrogio, Marco D. Sciuto, Donatella Dipartimento di Elettronica Informazione e Bioingegneria Politecnico di Milano Italy

ISBN: (纸本)9780769549798

Research efforts in Evolvable Hardware allowed to prove how it is possible to adopt a radically alternative approach to the synthesis of hardware circuits by drawing inspiration from natural selection and evolution. In order to move these achievements to a new level, however, we need more sophisticated tools and upport for experimenting with new structures and devices. This paper moves a first step in this direction by presenting our proposal for a holistic evolutionary framework, able to provide simple yet powerful abstractions o unify a variety of evolutionary architectures under the same comprehensive ramework. This way, we allow to reuse a finely-tuned evolutionary infrastructure for any kind of architecture using our general model. Additional contribution of this work is the design and evaluation, within the holistic framework, of a novel flexible fpga-based evolutionary architecture which dispenses from the need of relying on the internal configuration access port, which proved to be a serious bottleneck in previous work. © 2013 IEEE.

关键词： field programmable gate arrays (fpga)

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Comparametric HDR (High Dynamic Range) Imaging for Digital Eye Glass, Wearable Cameras, and Sousveillance

Comparametric HDR (High Dynamic Range) Imaging for Digital E...

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IEEE international symposium on Technology and Society (ISTAS)

作者： Ali, Mir Adnan Ai, Tao Gill, Akshay Emilio, Jose Ovtcharov, Kalin Mann, Steve Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

ISBN: (纸本)9781479912421;9781479909292

Wearable computing can be used to both extend the range of human perception, and to share sensory experiences with others. For this objective to be made practical, engineering considerations such as form factor, computational power, and power consumption are critical concerns. In this work, we consider the design of a low-power visual seeing aid, and how to implement computationally-intensive computational photography algorithms in a small form factor with low power consumption. We present realtime an fpga-based HDR (High Dynamic Range) video processing and filtering by integrating tonal and spatial information obtained from multiple different exposures of the same subject matter. In this embodiment the system captures, in rapid succession, sets of three exposures, " dark", " medium", and " light", over and over again, e. g. " dark", " medium", " light", " dark", " medium", " light", and so on, at 60 frames per second. These exposures are used to determine an estimate of the photoquantity every 1/60th of a second (each time a frame comes in, an estimate goes out). This allows us to build a seeing aid that helps people see better in high contrast scenes, for example, while welding, or in outdoor scenes, or scenes where a bright light is shining directly into the eyes of the wearer. Our system is suitable for being built into eyeglasses or small camera-based, lifeglogging, or gesturesensing pendants, and other miniature wearable devices, with low-power and compact circuits that can be easily mounted on the body.

关键词： digital photography field programmable gate arrays filtering theory image sensors video cameras video signal processing video surveillance visual perception wearable computers

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NBTI Life Time of a High Voltage PMOS FET

NBTI Life Time of a High Voltage PMOS FET

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20th IEEE international symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

作者： Jia, James Yingbo Xue, Fengliang Liu, Patty Tien, Jon Cai, Alex Dhaoui, Fethi Singaraju, Pavan Hawley, Frank McCollum, John Microsemi Corp San Jose CA 95134 USA

ISBN: (纸本)9781479904808;9781479912414

We present a study on NBTI life time for high voltage PMOS transistors. These devices are used in erasing and programming control circuits for a floating-gate flash based fpga array fabricated with a 65nm embedded process. NBTI stress tests were performed with different gate biases and at different temperatures. Life time model parameters, such as voltage acceleration factor and activation energy, were obtained from the tested results. NBTI device life time was assessed against product requirements. A 50 times (50X) margin in life time was estimated for our baseline process, based on DC stress data. Longer AC life time is seen due to recovery of device degradation. This allows even more margin for the real operation. Interface trap and positive charge contributions to the observed Vt shift were separated from a recovery study. It is observed that interface traps can be recovered either partially or completely depending on the recovery temperature. Positive charges can only be partially recovered at positive gate biases. To further improve NBTI lifetime margin against product requirement, LDD doping was increased and optimized We are able to further improve HV PIMOS device performance in this regard.

关键词： MOSFET field programmable gate arrays flash memories interface states negative bias temperature instability semiconductor device models semiconductor device reliability semiconductor device testing semiconductor doping stress analysis

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Fast Template-Based Heterogeneous MPSoC Synthesis on fpga

Fast Template-Based Heterogeneous MPSoC Synthesis on FPGA

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9th international Applied Reconfigurable Computing symposium (ARC)

作者： Corre, Youenn Diguet, Jean-Philippe Lagadec, Loic Heller, Dominique Blouin, Dominique Univ Bretagne Sud Lab STICC F-56100 Lorient France ENSTA Bretagne Lab STICC F-29200 Brest France

ISBN: (纸本)9783642368127;9783642368110

Our contribution lies in offering a fast and parametrized domain-space exploration to the designer, whose expertise drives the whole process while staying the actor of added-value creation. In this paper, we present two new features and two important improvements of our H-MPSoC synthesis framework. The first one is a new template-based approach for automated design space exploration and synthesis. A template describes an architecture model for a specific domain and has three levels of specifications each representing a different level of design expertise. We also rely on the Model-Driven Architecture (MDA) paradigm to provide flexibility, reusability and code generation for different fpga targets. We have refined the communication models to get more accurate performance estimations. Finally, we also improved our mapping decision algorithm that drastically reduces the simulation time. The output is the synthesizable code of the hardware architecture, the adapted C code of the application and the project files for fpga design tools. We use an MJPEG decoder as a case-study to validate our framework on a Xilinx fpga.

关键词： field programmable gate arrays (fpga)

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SW and HW Speculative Nelder-Mead Execution for High Performance Unconstrained Optimization

SW and HW Speculative Nelder-Mead Execution for High Perform...

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15th Annual international symposium on System-on-Chip (SoC)

作者： Mariano, Artur Garcia, Paulo Gomes, Tiago Tech Univ Darmstadt Inst Comp Sci Darmstadt Germany Univ Minho Cent Algoritmi Guimaraes Portugal

ISBN: (纸本)9781479911905

This paper addresses the performance assessment of a new Nelder-Mead variant, that speculatively executes the simplex operations. This new variant was implemented as x86 parallel and sequential CPU versions as well as in handwritten and automatic C-to-RTL fpga designs. As the execution flow is the same on every version, the efficiency of the synchronization by software and hardware is also accessed. Performance trials of these versions where performed using (i) a last-generation fpga and a last generation multi-core CPU-chip to run the software versions and (ii) relatively simple objective functions in R-2. Results show that performance of the handwritten hardware design is relatively equivalent to the sequential software version of the algorithm, even running at a much lower clock frequency (average of 1.9Mhz vs 3.4GHz). They also suggest that the synchronization methods employed to control the speculative execution are too expensive when managed by software, but efficient if managed by hardware.

关键词： software release executive stream computer software HIGH-PERFORMANCE Computer hardware speculative execution UNCONSTRAINED OPTIMISATION computer hardware design half-wave field programmable gate arrays Objective function computer programs Legal Executions PNPLA6 gene

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