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检索条件"任意字段=2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013"

共 809 条记录，以下是311-320 订阅

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HTR: On-Chip Hardware Task Relocation for Partially Reconfigurable fpgas

HTR: On-Chip Hardware Task Relocation for Partially Reconfig...

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9th international Applied Reconfigurable Computing symposium (ARC)

作者： Morales-Villanueva, Aurelio Gordon-Ross, Ann Univ Florida Dept Elect & Comp Engn NSF Ctr High Performance Reconfigurable Comp CHRE Gainesville FL 32611 USA

ISBN: (纸本)9783642368127;9783642368110

Partial reconfiguration (PR) enables shared fpga systems to nonintrusively time multiplex hardware tasks in partially reconfigurable regions (PRRs). To fully exploit PR, higher priority tasks should preempt lower priority tasks and preempted tasks should resume execution in any PRR. This preemption/resumption requires saving/restoring the preempted task's execution context and relocating the task to another PRR, however, prior works only provide partial solutions and impose limitations and/or overheads. We propose on-chip hardware task relocation (HTR) software, which enables a task's execution state to be saved, relocated to, and restored in any PRR with sufficient resources. The HTR software executes on a soft-core processor in the fpga's static region, and is thus portable across any system/application. Experimental results evaluate HTR execution times, enabling designers to tradeoff task/PRR granularity and HTR execution times based on application requirements.

关键词： field programmable gate arrays (fpga)

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Are fpgas suffering from the innovator's dilemna? 13

Are FPGAs suffering from the innovator's dilemna?

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Vaughn Betz Jason Cong University of Toronto Toronto ON Canada UCLA Los Angeles CA USA

ISBN: (纸本)9781450318877

fpgas constitute a highly profitable industry, with approximately $5 billion of sales per year. High barriers to entry keep most companies away, and enable high profit margins for the incumbents. The industry has grown greatly over the years, but still constitutes a small portion of the overall semiconductor market. This raises the question to be addressed by this panel: is the fpga community innovating as much as it should, or is a bias to maintain high profit margins and protect the cash flow of the current fpga market holding us back from exploring new ideas and products that could greatly expand the appeal of and market for fpga-related technology? This would be a classic case of the innovator's dilemma defined by Clayton Christensen: it is difficult for a company to engage in creative destruction of a cash cow *** distinguished panel of experts will discuss whether we are seeing major innovation in architectures, design flows and applications, or only incremental improvements. We will also discuss if any new (possibly low margin) application domain is left out by the fpga industry, what radical ideas should be explored, and whether large incumbents, new startups, academia or some combination are best able to attack these new areas.

关键词： field programmable gate arrays

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Stream-mode fpga acceleration of complex pattern trajectory querying

Stream-mode FPGA acceleration of complex pattern trajectory ...

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13th international symposium on Spatial and Temporal Databases, SSTD 2013

作者： Moussalli, Roger Vieira, Marcos R. Najjar, Walid Tsotras, Vassilis J. University of California Riverside CA United States IBM Research Brazil

ISBN: (纸本)9783642402340

The wide and increasing availability of collected data in the form of trajectory has lead to research advances in behavioral aspects of the monitored subjects (e.g., wild animals, people, vehicles). Using trajectory data harvested by devices, such as GPS, RFID and mobile devices, complex pattern queries can be posed to select trajectories based on specific events of interest. In this paper, we present a study on fpga-based architectures processing complex patterns on streams of spatio-temporal data. Complex patterns are described as regular expressions over a spatial alphabet that can be implicitly or explicitly anchored to the time domain. More importantly, variables can be used to substantially enhance the flexibility and expressive power of pattern queries. Here we explore the challenges in handling several constructs of the assumed pattern query language, with a study on the trade-offs between expressiveness, scalability and matching accuracy. We show an extensive performance evaluation where fpga setups outperform the current state-of-the-art CPU-based approaches by over three orders of magnitude. Unlike software-based approaches, the performance of the proposed fpga solution is only minimally affected by the increased pattern complexity. © 2013 Springer-Verlag.

关键词： field programmable gate arrays (fpga)

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IEEE1588 V2 clock distribution in FlexRIO devices: Clock drift measurement

IEEE1588 V2 clock distribution in FlexRIO devices: Clock dri...

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19th IMEKO TC4 symposium - Measurements of Electrical Quantities 2013 and 17th international Workshop on ADC and DAC Modelling and Testing

作者： Sanz, D. Ruiz, M. Lopez, J.M. Castro, R. Vega, J. Barrera, E. Grupo de Investigación en Instrumentación y Acústica Aplicada Universidad Politécnica de Madrid Madrid Spain Asociacion EURATOM/CIEMAT Madrid Spain

ISBN: (纸本)9781629931890

Instrumentation in scientific experiments requires highest accurate to correlate acquired data with a time reference. In order to implement data acquisition channels synchronized to a reference clock, it is necessary to deploy a distributed clock based on computer devices with specific hardware for data acquisition, and to use a technology capable of synchronizing every computer in the system. Although there are several technologies to synchronize devices as the Precision Time Protocol (PTP) IEEE1588 V2 [1], not always is trivial to use it to get a good performance. This work studies how can be used the drift measures between clocks to get them synchronized. The solution has been implemented using a PTP-clock (implemented in a IEEE1588 PXI device), to every PXI/PXIe [2] and the fpga based FlexRIO devices [3], able to reconfigure its hardware. The PXI/PXIe bus will be the key element to propagate the clock from the timing board to every RIO/FlexRIO card, achieving to phase their internal clocks with the PTP.

关键词： field programmable gate arrays (fpga)

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Hardware Acceleration of the Robust Header Compression (RoHC) Algorithm

Hardware Acceleration of the Robust Header Compression (RoHC...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： Al-Obaidi, Mohammed Kittur, Harshavardhan Andersson, Hakan Owall, Viktor Lund Univ Dept Elect & Informat Technol Box 118 SE-22100 Lund Sweden Ericsson AB FJL MT SE-58112 Linkoping Sweden

ISBN: (纸本)9781467357623;9781467357609

In LTE base-stations, RoHC is a processing-intensive algorithm that may limit the system from serving a large number of users when it is used to compress the VoIP packets of mobile traffic. In this paper, a hardware-software and a full-hardware solution are proposed to accelerate the RoHC compression algorithm in LTE base-stations and enhance the system throughput and capacity. Results for both solutions are discussed and compared with respect to design metrics like throughput, capacity, power consumption, and hardware resources. This comparison is instrumental in taking architectural level trade-off decisions in-order to meet the present day requirements and also be ready to support a future evolution. In terms of throughput, a gain of 20% (6250 packets/sec) is achieved in the HW-SW implementation by accelerating the Cyclic Redundancy Check (CRC) and the Least Significant Bit (LSB) encoding in hardware. The full-HW implementation leads to a throughput of 45 times (244000 packets/sec) compared to the SW-Only implementation. The full-HW solution consumes more Adaptive Look-Up Tables (7477 ALUTs) compared to the HW-SW solution (2614 ALUTs) when synthesized on Altera's Arria II GX fpga.

关键词： Internet telephony Long Term Evolution cyclic redundancy check codes field programmable gate arrays telecommunication traffic

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Partial LUT Size Analysis in Distributed Arithmetic FIR Filters on fpgas

Partial LUT Size Analysis in Distributed Arithmetic FIR Filt...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： Kumm, Martin Moeller, Konrad Zipf, Peter Univ Kassel Digital Technol Grp Kassel Germany

ISBN: (纸本)9781467357623;9781467357609

Distributed arithmetic is a popular method for implementing digital FIR filters on fpgas. One essential optimization method is the division of large look-up tables (LUTs) into smaller partial LUTs by using additional adders. Previous work indicates, that the size of these partial LUTs should be chosen to the LUT input size of the fpga which was 4 for a long time. Nowadays, modern fpgas offer 6-input LUTs which can be configured to two 5-input LUTs with shared inputs. This paper investigates the optimal input size of partial LUTs on fpgas with 4-input and 5/6-input LUTs. On fpgas with 4-input LUTs, it turnes out that only in 62% of the cases (out of 220), a LUT input size of 4 leads to the best implementation. However, the slice overhead is 6.3% on average for the other cases. On fpgas with 5/6-input LUTs, the least slice overhead (10% on average) is paid when the LUT input size is chosen to 6. However, it was shown that a resource reduction of up to 32% can be achieved when all input sizes in the range 4...7 are evaluated. Using the best partial LUT size, slice reductions of over 50% on average compared to Xilinx Coregen could be achieved for Virtex 6 fpgas.

关键词： FIR filters adders distributed arithmetic field programmable gate arrays optimisation table lookup

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Localized Electromagnetic Analysis of RO PUFs

Localized Electromagnetic Analysis of RO PUFs

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IEEE international symposium on Hardware-Oriented Security and Trust (HOST)

作者： Merli, Dominik Heyszl, Johann Heinz, Benedikt Schuster, Dieter Stumpf, Frederic Sigl, Georg Fraunhofer Res Inst Appl & Integrated Secur AISEC Munich Germany Tech Univ Munich Inst Secur Informat Technol Munich Germany

ISBN: (纸本)9781479906017;9781479905591

Among all proposed Physical Undo able Fll nelions (PUFs), those based on Ring Oscillators (ROs) are a popular solution for ASICs as well as for fpgas. However, compared to other PIM architectures, oscillators emit electromagnetic (EM) signals over a relatively long run time, which directly reveal their unique frequencies. Previous work by Merli et al. exploited this fact by global EM measurements and proposed a countermeasure for their attack. In this paper, we first demonstrate that it is feasible to measure and locate the EM emission of a single tiny RO consisting of only three inverters, implemented within a single configurable logic block of a Xilinx Spartan-3A. Second, we present a localized EM attack for standard and protected RO PUFs. We practically investigate the proposed side-channel attack on a protected fpga RO PUN implementation. We show that RO PUI's are prone to localized EM attacks and propose two countermeasures, namely, randomization of RO measurement logic and interleaved placement.

关键词： application specific integrated circuits field programmable gate arrays integrated circuit design integrated circuit measurement integrated circuit testing invertors oscillators

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A Layout-Aware Test Methodology for Silicon Interposer in 3D System-in-a-Package

A Layout-Aware Test Methodology for Silicon Interposer in 3D...

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IEEE 2nd international symposium on Next-Generation Electronics (ISNE)

作者： Gu, Ruei-Ting Ho, Cheng-You Li, Katherine Shu-Min Ho, Yingchieh Chen, Liang-Bi Hsieh, Kai-Yang Huang, Jiun-Jie Cheng, Bo-Chuan Wang, Sying-Jyan Gao, Zih-Huan Natl Sun Yat Sen Univ Dept Comp Sci & Engn Kaohsiung 80424 Taiwan ASE Grp Kaohsiung Taiwan Natl Chiao Tung Univ Dept Elect Engn Hsinchu Taiwan BXB Elect Co Ltd Kaohsiung Taiwan Natl Chung Hsing Univ Dept Comp Sci & Engn Taichung Taiwan Natl Sun Yat Sen Univ Dept Elect Engn Kaohsiung Taiwan

ISBN: (纸本)9781467330374;9781467330367

In this paper, we propose an efficient silicon interposer pre-test methodology, which is based on the layout-aware ripple baseline algorithm for System-in-a-Package (SiP). The proposed methodology uses fpga as our test vehicle that can test all interconnects at once without any test probes. The test interposer is synthesized according to the given layout of the target interposers, which provide microbumps and solder balls with pitches, and the test interposers are connected to the upper test side of the target interposers. Thus the test loops, which cover all interconnections of the target interposers, are built by connecting the test interposers and the target interposers. The bottom side of the target interposer is connected to an fpga as the tester that provides test patterns to the target interposer and compares the result to identify the faulty interconnections of the target interposer. Experimental results show our method is both effective and efficient with achieving 100% fault coverage for all interposers. With scaling to more than hundreds of hundreds interposers, our method is still effective within two to three hours.

关键词： field programmable gate arrays integrated circuit interconnections integrated circuit layout solders system-in-package three-dimensional integrated circuits

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On improving at no cost the quality of products built with SRAM-based fpgas

On improving at no cost the quality of products built with S...

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5th Asia symposium on Quality Electronic Design, ASQED 2013

作者： Leveugle, R. Ben Jrad, M. TIMA Laboratory Grenoble INP UJF CNRS 46 Av. Félix Viallet 38031 Grenoble Cedex France

ISBN: (纸本)9781479913145

Product or design quality encompasses many aspects. One of them is the robustness with respect to perturbations. This robustness depends on the implementation technology, but can also be improved at design time. This paper is focused on designs implemented in SRAM-based fpgas that are sensitive to soft errors in the configuration memory. An approach is proposed to increase the dependability with respect to configuration errors, at no cost, by selectively hardening parts of the design. The selection of locally duplicated functions is made so that the protections take advantage of fpga resources that would not be used by the implemented design. An automated design flow is presented for Xilinx Virtex V devices and fault injection results show that the design dependability may be noticeably enhanced. As an example, more than 40% of the LUTs used to implement a Leon3 Sparc v8 processor can be protected against multiple configuration errors with less than 20% resource overheads at the block level. The final system-level overhead may in many cases be null for a given product, either due to the discrete sizes of available fpgas or to a different repartition of resource budget between system blocks. © 2013 IEEE.

关键词： field programmable gate arrays (fpga)

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Indirect connection aware attraction for fpga clustering (abstract only) 13

Indirect connection aware attraction for FPGA clustering (ab...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Meng Yang Jiarong Tong A.E.A. Almaini State Key Lab of ASIC Fudan University Shanghai China Edinburgh Napier University Edinburgh United Kingdom

ISBN: (纸本)9781450318877

Indirect connection aware attraction clustering algorithm is proposed for clustered field programmable gate array architecture model to achieve simultaneously optimization of several performance metrics. A new cost function considers the attraction of the subsequent basic logic elements (BLEs) to the selected cluster, the number of the used pins already in the cluster, as well as critical path delay. The attractions of which BLEs are directly and indirectly connected to the selected cluster are taken into account. As a result, more external nets are absorbed into clusters, less number of pins per cluster and fewer clusters are required. Hence, smaller channel width is required for routing and speed of the design is improved. Performance comparisons are carried out in details with respect to state-of-the-art clustering techniques interconnect resource aware clustering (iRAC) and many-objective clustering (MO-Pack). Results show that the proposed algorithm outperforms these two clustering approaches with achievements of 38.8% and 42.2% respectively in terms of channel widths and 40.1% and 44.8% respectively in terms of number of external nets but with no critical path and area overhead.

关键词： fpgas computer aided design clustering optimization field-programmable gate arrays

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