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检索条件"任意字段=2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013"

共 809 条记录，以下是331-340 订阅

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fpga-Based Implementation of the Back-EMF Symmetric-Threshold-Tracking Sensorless Commutation Method for Brushless DC-Machines

FPGA-Based Implementation of the Back-EMF Symmetric-Threshol...

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IEEE international symposium on Sensorless Control for Electrical Drives and Predictive Control of Electrical Drives and Power Electronics (SLED/PRECEDE)

作者： Darba, Araz De Belie, Frederik Salem, Aboubakr Melkebeek, Jan Univ Ghent Dept Elect Energy Syst & Automat St Pietersnieuwstr 41 B-9000 Ghent Belgium

ISBN: (纸本)9781479906802

The operation of brushless DC permanent-magnet machines requires information of the rotor position to steer the semiconductor switches of the power-supply module which is commonly referred to as Brushless Commutation. Different sensorless techniques have been proposed to estimate the rotor position using current and voltage measurements of the machine. Detection of the back-electromotive force (EMF) zero-crossing moments is one of the methods most used to achieve sensorless control by predicting the commutation moments. Most of the techniques based on this phenomenon have the inherit disadvantage of an indirect detection of commutation moments. This is the result of the commutation moment occurring 30 electrical degrees after the zero-crossing of the induced back-emf in the unexcited phase. Often, the time difference between the zero crossing of the back-emf and the optimal current commutation is assumed constant. This assumption can be valid for steady-state operation, however a varying time difference should be taken into account during transient operation of the BLDC machine. This uncertainty degrades the performance of the drive during transients. To overcome this problem which improves the performance while keeping the simplicity of the back-emf zero-crossing detection method an enhancement is proposed. The proposed sensorless method operates parameterless in a way it uses none of the brushless dc-machine parameters. In this paper different aspects of experimental implementation of the new method as well as various aspects of the fpga programming are discussed. Proposed control method is implemented within a Xilinx Spartan 3E XC3S500E board.

关键词： Permanent-magnet brushless DC-machine (BLDC-machine) back-EMF zero-crossing sensorless control field-programmable gate arrays (fpgas)

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Package technology selection of 28nm high power fpga with Pb-free solder bumps: Flip chip molded BGA (FCMBGA) versus traditional flip chip bare die package

Package technology selection of 28nm high power FPGA with Pb...

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46th Annual IMAPS international symposium on Microelectronics, IMAPS 2013

作者： Lyakas, Michael Reichman, Corey Jimarez, Miguel Ocampo, Romina Mimi Elberg, Aaron Hasan, Altaf Hale, Dierdre Hamilton, Fred Kim, Joon Dong Amkor Technology 1900 South Price Road Chandler AZ 85286 United States

ISBN: (纸本)9781629938240

Selecting the optimal flip-chip package technology for the next generation 28nm fpga is critical not only to meet reliability benchmarks for Pb-free bumps, but also in meeting the field-use environment requirements for high power devices. Component level reliability testing was conducted on three separate package types: Bare die flip chip BGA (FCBGA), flip chip molded BGA with capillary underfill (FCMBGA w/CUF), and flip chip molded BGA with molded underfill. (FCMBGA). Testing was conducted independently at two separate sites. Testing included moisture resistance testing (MRT), temperature cycle (JESD22-A104 Condition Level B), and a hybrid test combining 100 hours of unbiased HAST (JESD22-A118A) with temperature cycling. Reliability monitoring was conducted through multiple means including electrical testing for circuit continuity, CSAM imaging at frequent read points to monitor silicon integrity and underfill adhesion performance, cross-sections for the inspection of bump crack propagation, and FIB analysis of the UBM structure after test completion. In addition to reliability testing of three flip chip BGA platforms, other usage factors were considered. These include package specific design rule flexibility for passive placement and future generation packaging requirements. The results of the evaluation demonstrated that bump integrity remained strong for all three package types - showing no cracks after 1, 500 temperature cycles, hybrid testing, or MRT. Ultimately, the FCMBGA with molded underfill was selected based on the quality of the bumps after testing, the design rule flexibility for capacitor placement, and improved component protection from mechanical damage.

关键词： field programmable gate arrays (fpga)

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A Flexible Interconnection Structure for Reconfigurable fpga Dataflow Applications

A Flexible Interconnection Structure for Reconfigurable FPGA...

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IEEE international symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Gianluca Durelli Alessandro A. Nacci Riccardo Cattaneo Christian Pilato Donatella Sciuto Marco D. Santambrogio Dipartimento di Elettronica Politecnico di Milano Milano Italy

ISBN: (纸本)9781479913725

Dataflow applications have proven to be well-suited for hardware implementation due to their intrinsic pipelined nature. Furthermore a wide range of algorithms, ranging from image analysis to map-reduce tasks, can be expressed using this paradigm. At the same time field programmable gate arrays (fpga) start to be employed as hardware accelerators also in high-end systems coupled with General Purpose Processors (GPP). In this work we propose a programmable interconnection structure which permits to dynamically reconfigure the functionality of an fpga implementing dataflow applications. A detailed analysis of the proposed solution shows that it is effectively able to increase the overall system flexibility helping in reducing the overall workload execution up to 25%, while at the same time reducing its variance.

关键词： Kernel Hardware field programmable gate arrays Pipelines arrays Switches

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Efficient hough transform on the fpga using DSP slices and block RAMs

Efficient hough transform on the FPGA using DSP slices and b...

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2013 IEEE 37th Annual Computer Software and Applications Conference, COMPSAC 2013

作者： Zhou, Xin Tomagou, Norihiro Ito, Yasuaki Nakano, Koji Department of Information Engineering Hiroshima University Kagamiyama 1-4-1 Higashi Hiroshima 739-8527 Japan

ISBN: (纸本)9780769549798

The main contribution of this paper is to present a new fpga architecture for the Hough transform that identifies straight lines in a binary image. Recent fpgas have hundreds of embedded DSP slices and block RAMs. For example, Xilinx Virtex-6 Family fpgas have a DSP48E1 slice, which is a configurable logic block equipped with fast multipliers, adders, pipeline registers, and so on. They also have a dual-port memory with 18Kbits as a block RAM. One of the most important key techniques for accelerating computation using fpgas is an efficient usage ofDSP slices and block RAMs. Our new architecture for the Hough transform uses 178~DSP48E1 slices and 180~block RAMs with 18Kbits that work in parallel. As far as we know, there is no previously published work that fully utilizes DSP slices and block RAMs for the Hough transform. Roughly speaking, a conventional sequential implementation performs 180m voting operations for m edge points. Our architecture performs voting operations in parallel, and outputs identified straight lines in m+97 clock cycles. Since 180m voting operations are performed using 178 DSP48E1 slices, the lower bound of the computing time is m clock cycles. Hence our implementation is close to optimal. The implementation results show that the Hough transform for a 512x512 image with 33232 edge points can be done in only 135. 75us. © 2013 IEEE.

关键词： field programmable gate arrays (fpga)

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Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications

Heterogeneous Reconfigurable System for Adaptive Particle Fi...

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9th international Applied Reconfigurable Computing symposium (ARC)

作者： Chau, Thomas C. P. Niu, Xinyu Eele, Alison Luk, Wayne Cheung, Peter Y. K. Maciejowski, Jan Univ London Imperial Coll Sci Technol & Med Dept Comp London SW7 2AZ England London Imperial Coll Dept Elect Elect Engn London SW7 2AZ England Univ Cambridge Dept Engn Cambridge CB2 1TN England

ISBN: (纸本)9783642368127;9783642368110

This paper presents a heterogeneous reconfigurable system for real-time applications applying particle filters. The system consists of an fpga and a multi-threaded CPU. We propose a method to adapt the number of particles dynamically and utilise the run-time reconfigurability of the fpga for reduced power and energy consumption. An application is developed which involves simultaneous mobile robot localisation and people tracking. It shows that the proposed adaptive particle filter can reduce up to 99% of computation time. Using run-time reconfiguration, we achieve 34% reduction in idle power and save 26-34% of system energy. Our proposed system is up to 7.39 times faster and 3.65 times more energy efficient than the Intel Xeon X5650 CPU with 12 threads, and 1.3 times faster and 2.13 times more energy efficient than an NVIDIA Tesla C2070 GPU.

关键词： field programmable gate arrays (fpga)

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Upgrade of the ATLAS Level-1 trigger with an fpga based Topological Processor

Upgrade of the ATLAS Level-1 trigger with an FPGA based Topo...

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60th IEEE Nuclear Science symposium (NSS) / Medical Imaging Conference (MIC) / 20th international Workshop on Room-Temperature Semiconductor X-ray and Gamma-ray Detectors

作者： Caputo, Regina Bauss, Bruno Buscher, Volker Degele, Reinhold Kiese, Patric Maldaner, Stephan Reiss, Andreas Schaefer, Ulrich Simioni, Eduard Tapprogge, Stefan Urrejola, Pedro Johannes Gutenberg Univ Mainz Mainz Germany

ISBN: (纸本)9781479905348

The ATLAS experiment is located at the European Centre for Nuclear Research (CERN) in Switzerland. It is designed to measure decay properties of highly energetic particles produced in the protons collisions at the Large Hadron Collider (LHC). The LHC has a beam collision frequency of 40 MHz, and thus requires a trigger system to efficiently select events, thereby reducing the storage rate to a manageable level of about 400 Hz. Event triggering is therefore one of the extraordinary challenges faced by the ATLAS detector. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 75kHz and decision latency of less than 2.5 mu s. It is primarily composed of the Calorimeter Trigger, Muon Trigger, the Central Trigger Processor (CTP). Due to the increase in the LHC instantaneous luminosity up to 3x10(34) cm(-2) s(-1) from 2015 onwards, a new element will be included in the Level-1 Trigger scheme: the Topological Processor (L1Topo). The L1Topo receives data in a specialized format from the calorimeters and muon detectors to be processed by specific topological algorithms. Those algorithms sit in high-end fpgas which perform geometrical cuts, correlations and calculate complex observables such as the invariant mass. The outputs of such topological algorithms are sent to the CTP. Since the Level-1 trigger is a fixed latency pipelined system, the main requirements for the L1Topo are a large input bandwidth (approximate to 1Tb/s), optical connectivity and low processing latency on the real-time data path. This presentation focuses on the design of the L1Topo final production module and the tests results on L1Topo prototypes. Such tests are aimed at characterizing high-speed links (signal integrity, bit error rate, margin analysis and latency) and the logic resource utilization of algorithms.

关键词： field programmable gate arrays (fpga)

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A Hybrid CBRAM/CMOS Look-Up-Table structure for improving performance efficiency of field-programmable-gate-Array

A Hybrid CBRAM/CMOS Look-Up-Table structure for improving pe...

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IEEE international symposium on Circuits and Systems

作者： Santhosh Onkaraiah Ogun Turkyilmaz Marina Reyboz Fabien Clermidy Elisa Vianello Jean-Michel Portal Christophe Muller CEA-LETI MINATEC Grenoble France IM2NP UMR CNRS 6242 Aix-Marseille Universite Marseille France

ISBN: (纸本)9781467357609

At most advanced technology nodes, field programmable gate arrays (fpga) present great advantages compared to more conventional processor architectures;their natural regularity, modularity and inherent reliability due to duplicated identical tiles provide a solution to overcome new technologies with increasing variability. However, fpga market is still limited by power efficiency issue, due to two coordinated factors like interconnection-dominated design and large usage of memories, computation being performed thanks to Look-Up-Table (LUT). In this paper, we propose a solution to improve the performance and reduce the power consumption of LUT in fpga using CBRAM-based structures. Our proposed design shows significant improvement compared to the traditional SRAM-based fpga in: a) critical delay is reduced by ～23% due to compact structure (1T-2R) and b) power gain by reduction in static power consumption by ～18%.

关键词： CBRAM NV-RAM NV-fpga compact model resistive memory LUT field programmable gate arrays Power consumption Lower Urinary Tract Symptoms Processor Architectures new technology Solutions

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fpga memory testing technique using BIST

FPGA memory testing technique using BIST

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Midwest symposium on Circuits and Systems (MWSCAS)

作者： Priyanka Gadde Mohammed Niamat Electrical Engineering and Computer Science Department The University of Toledo Toledo Ohio USA

The wide use of field programmable gate arrays (fpgas) in critical applications including, military and airborne applications require fault free operation of the fpga. In fpgas, faults can occur in the memory resources, logic blocks, or the interconnects. In this paper, memory faults including Stuck-at, Transition, Address Decoder, Incorrect Read, Deceptive Read Destructive, and Data Retention Faults are analyzed using an optimized March C- algorithm. In order to evaluate the effectiveness of this algorithm, a novel Built-in Self Test (BIST) technique to test the embedded SRAM memory of the fpga is proposed. The proposed technique reduces the test time by approximately half as compared to previously published schemes. The fpga is modeled in VHDL at the equivalent gate level and the simulations results are generated using ModelSim.

关键词： Circuit faults Built-in self-test field programmable gate arrays Random access memory Table lookup

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Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on fpga (abstract only) 13

Hybrid masking using intra-masking dual-rail memory on LUT f...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Anh-Tuan Hoang Takeshi Fujino Ritsumeikan University Shiga prefecture Kusatsu city Japan

ISBN: (纸本)9781450318877

In current countermeasure design trends against Different Power Analysis (DPA), security at gate level is required in addition to the security algorithm. Several Dual-rail pre-charge logics (DPL) have been proposed to achieve this goal. Designs using ASIC can attain this goal owing to its backend design restrictions on placement and routing. However, implementing these designs on field programmable gate Array (fpga) without information leakage is still a problem because of the difficulty involved in the restrictions on placement and routing on fpga. This paper describes our novel Hybrid Masking implementations using Intra-Masking Dual-rail Memory (IMDRM) approach for Side-channel-resistant AES. The hybrid masking scheme includes an additive mask and a multiplicative mask. The additive masking scheme utilizes a dual-rail memory, in which all unsafe nodes, such as unmasking and masking, the dual-rail memory and buses are packed into a single LUT. This makes them balanced and independent of the placement and routing tools. The multiplicative masking scheme is then applied over the additive masked values. It removes the joint-leakage, which is caused by the joint processing of the masks and the masked values inside the dual-rail memory. The design is independent of the cryptographic algorithm and persistent with SCA attacks even after 1,000,000 traces. It also occupied smaller hardware size than most other advanced SCA resistant implementations such as the Wave Dynamic Differential Logic, the Masked Dual-Rail Pre-charge Logic, and the Intra-Masking Dual-Rail Memory.

关键词： SCA resistance differential power analysis (DPA) side-channel attack masking intra-masking dual-rail memory on LUT dual-rail memory field programmable gate array (fpga) hybrid masking AES

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A Fast and Accurate fpga-Based Fault Injection System

A Fast and Accurate FPGA-Based Fault Injection System

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Annual IEEE symposium on field-programmable Custom Computing Machines (FCCM)

作者： Thomas Schweizer Dustin Peterson Johannes M. Kühn Tommy Kuhn Wolfgang Rosenstiel Computer Engineering Wilhelm-Schickard Institute Faculty of Science Eberhard Karls Universität Tübingen Tubingen Germany

This paper introduces an fpga-based fault injection system. To realize this system a library was developed, which implements a static mapping between a circuit described at RTL or gate-level and its corresponding placed and routed fpga design. The aim of this mapping is to preserve module and port structure of the placed and routed fpga design to the RT/gate-level circuit description. To demonstrate the accuracy of this mapping the ISCAS'89 benchmark circuits and the VHDL netlist of the LEON3 system are used. The results show that about 99% of the ports in the RT/gate-level circuit description can be located in the placed and routed fpga design. Based on this library a fault injection tool was developed to accelerate the fault injection experiment time by bypassing some stages (synthesis, placement and routing) of a re-compilation process. In these experiments a 12 × speedup was achieved when compared to fault injections based on serial fault emulation.

关键词： Circuit faults field programmable gate arrays Emulation Logic gates Hardware Libraries Ports (Computers)

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