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检索条件"任意字段=2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013"

共 809 条记录，以下是381-390 订阅

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Design and implementation of LMS adaptive filter algorithm based on fpga

Design and implementation of LMS adaptive filter algorithm b...

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international symposium on Instrumentation & Measurement, Sensor Network and Automation (IMSNA)

作者： Guanghui Cai Jun Yang Chuan Liang Hongye Li School of Information Science and Engineering Yunnan University Kunming Yunnan China

In the occasion of real-time requirements and harsh electromagnetic environments, currently adaptive filtering algorithm is most based on the DSP chip, using of Assembly Language and high-level language programming procedures, and the speed of processing and the performance of noise immunity are not match the requirement. LMS adaptive filter is a widely used digital signal processing algorithms. Due to the high flexibility and the high integrated of fpga technology, this paper propose a LMS algorithm using fpga technology to achieve it, and well used in adaptive filter, not only meet the needs of flexibility and real-time for systems, but also easy to implement, compared with other algorithms it is more simple and more reliable. It has good prospects in the field of signal processing.

关键词： Adaptive filters Least squares approximations field programmable gate arrays Signal processing algorithms Educational institutions Real-time systems Algorithm design and analysis

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fpga implementation of parallel unitary-rotation Jacobi EVD method based on Network-on-Chip

FPGA implementation of parallel unitary-rotation Jacobi EVD ...

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IEEE international symposium on Intelligent Signal Processing and Communication Systems (ISPACS)

作者： Chi-Chia Sun Juergen Goetze Department of Electronic Engineering National Formosa University Huwei Taiwan

In this paper, a new design concept for accelerating parallel Jacobi method by using Network-on-Chip (NoC) is presented. The implementation of the Brent-Luk-EVD array is used as an example. In order to further study the tradeoff between the performance/complexity of EVD processors and the load/throughput of interconnects, a mesh structure NoC design based Jacobi EVD array with the simplified μ-CORDIC processor PE has be implemented on fpga. The hardware experimental results show that using a NoC architecture makes it able to deal with large-scale size EVD problem and reduce the computation time.

关键词： field programmable gate arrays Jacobian matrices Calculators Adders Multiplexing

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Performance evaluation of fpga based embedded ARM processor for ultrasonic imaging

Performance evaluation of FPGA based embedded ARM processor ...

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IEEE symposium (IUS) Ultrasonics

作者： Spenser Gilliland Pramod Govindan Thomas Gonnot Jafar Saniie Department of Electrical and Computer Engineering Illinois Institute of Technology Chicago IL U.S.A.

ISBN: (纸本)9781467356855

This study evaluates the performance of an fpga based embedded ARM processor system to implement signal processing for ultrasonic imaging and nondestructive testing applications. fpga based embedded processors possess many advantages including a reduced overall development time, increased performance, and the ability to perform hardware-software (HW/SW) co-design. This study examines the execution performance of split spectrum processing, chirplet signal decomposition, Wigner-Ville distributions and short time Fourier transform implementations, on two embedded processing platforms: a Xilinx Virtex-5 fpga with embedded MicroBlaze processor and a Xilinx Zynq fpga with embedded ARM processor. Overall, the Xilinx Zynq fpga significantly outperforms the Virtex-5 based system in software applications.

关键词： Acoustics field programmable gate arrays Signal processing algorithms Chirp System-on-chip Time-frequency analysis Signal resolution

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Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices

Escaping the Academic Sandbox: Realizing VPR Circuits on Xil...

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Annual IEEE symposium on field-programmable Custom Computing Machines (FCCM)

作者： Eddie Hung Fatemeh Eslami Steven J.E. Wilton Department of Electrical and Computer Engineering University of British Columbia Vancouver Canada

This paper presents a new, open-source method for fpga CAD researchers to realize their techniques on real Xilinx devices. Specifically, we extend the Verilog-To-Routing (VTR) suite, which includes the VPR place-and-route CAD tool on which many fpga innovations have been based, to generate working Xilinx bitstreams via the Xilinx Design Language (XDL). Currently, we can faithfully translate VPR's heterogeneous packing and placement results into an exact Xilinx `map' netlist, which is then routed by its `par' tool. We showcase the utility of this new method with two compelling applications targeting a 40nm Virtex-6 device: a fair comparison of the area, delay, and CAD runtime of academia's state-of-the-art VTR How with a commercial, closed-source equivalent, along with a CAD experiment evaluated using physical measurements of on-chip power consumption and die temperature, over time. This extended How - VTR-to-Bitstream - is released to the community with the hope that it can enhance existing research projects as well as unlock new ones.

关键词： field programmable gate arrays Video recording Design automation Hardware design languages Routing Table lookup Digital signal processing

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FAssem: fpga Based Acceleration of De Novo Genome Assembly

FAssem: FPGA Based Acceleration of De Novo Genome Assembly

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Annual IEEE symposium on field-programmable Custom Computing Machines (FCCM)

作者： B. Sharat Chandra Varma Kolin Paul M. Balakrishnan Dominique Lavenier Department of Computer Science and Engineering Indian Institute of Technology Delhi New Delhi India INRIA IRISA Rennes France

Next generation sequencing technologies produce large amounts of data at very low cost. They produce short reads of DNA fragments. These fragments have many overlaps, lots of repeats and may also include sequencing errors. The assembly process involves merging these sequences to form the original sequences. In recent years many software programs have been developed for this purpose. All of them take significant amount of time to execute. Velvet is a commonly used de novo assembly program. We propose a method to reduce the overall time for assembly by using pre-processing of the short read data on fpgas and processing its output using Velvet. We show significant speed-ups with slight or no compromise on the quality of the assembled output.

关键词： field programmable gate arrays Assembly Bioinformatics Software Genomics Acceleration Redundancy

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Exploring Manycore Multinode Systems for Irregular Applications with fpga Prototyping

Exploring Manycore Multinode Systems for Irregular Applicati...

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Annual IEEE symposium on field-programmable Custom Computing Machines (FCCM)

作者： Marco Ceriani Gianluca Palermo Simone Secchi Antonino Tumeo Oreste Villa DEIB Politecnico di Milano Milano Italy DIEE Università di Cagliari Cagliari Italy Pacific Northwest National Laboratory Richland WA USA

We propose an intermediate approach between full custom hardware systems and full-software tools. Figure 1 shows the overview of the proposed architecture. We start from an off-the-shelf architecture composed of simple, in-order cores and an on-chip interconnection. The onchip interconnection interfaces the processing core with the memory controller for the external memory (DDR3) and the shared I/O peripherals. We add three custom components: the Global Memory Access Scheduler (GMAS), the Global Network Interface (GNI) and the Global SYNChronization module (GSYNC). The GMAS enables support for the scrambled address space. It also implements part of the support latency tolerance, storing remote memory operations, and acts as a scheduler for lightweight software multithreading.

关键词： Computer architecture Synchronization Random access memory field programmable gate arrays Software Switches Hardware

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fpga implementation of the m-ary modular exponentiation

FPGA implementation of the m-ary modular exponentiation

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international Design and Test Workshop

作者： Anane Nadjia Anane Mohamed CDTA (Centre de Développement des Technologies Avancées) Algiers Algeria ESI (Ecole nationale Supérieure d'Informatique) Algiers Algeria

Modular exponentiation is a key operation of RSA cryptosystem and is very time consuming for large operands. It is performed using successive modular multiplications. This paper describes hardware architecture of the m-ary modular exponentiation with reduced number of Montgomery modular multiplications. This architecture has been implemented on fpga circuit of Virtex-2 and presents best performances in terms of computation time and occupied resources.

关键词： field programmable gate arrays Hardware Multiplexing Cryptography Complexity theory Memory management

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High throughput multi pipeline packet classifier on fpga

High throughput multi pipeline packet classifier on FPGA

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CSI international symposium on Computer Architecture and Digital Systems

作者： Rashid Isvand Khatami Mahmood Ahmadi Department of Computer Engineering Razi University Kermanshah Iran

Packet classification is one of the most important functions in the router design. This is to support a variety of network functionalities. Pipeline-based decision tree is one of the best choices for increasing throughput on packet classification. SRAM-based and hardware-based solutions are often used to develop a high speed packet classification engine. However, SRAM-based solutions suffer from throughput degradation, delay variation and memory overflow. Moreover, hardware-based solutions suffer from fast update and non-linear structure. To address these problems, we propose a fpga-based multipipeline architecture for 5-tuple rules into multiple subsets to build a decision tree with high throughput and fast update. To fit the current largest rule set in the fpga device, we propose several optimization techniques, so that maximize the resource utilization while sustaining high throughput. In this architecture Look Up Tables (LUTs) are used instead of memory blocks. Partial reconfiguration in field programmable gate Array (fpga) used to reduce the time that is needed to change the behavior of architecture. The implementation results show that our architecture can store over 10K real-life rules in LUTs of a single Xilinx Virtex-6 fpga, and sustain over 120 Gbps (i.e. 3× OC-768 rate) throughput for minimum size (40 Bytes) packets.

关键词： Pipelines field programmable gate arrays Throughput Computer architecture Decision trees Engines Logic gates

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Dual glucose/cholesterol meter applications based on fpga platform

Dual glucose/cholesterol meter applications based on FPGA pl...

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international symposium on Next-Generation Electronics (ISNE)

作者： Teddy Lesmana Wen-Yaw Chung Shih-Lun Chen Lu-Chiang Hung Department of Electronic Engineering Chung Yuan Christian University Chung Li Taiwan

In this paper, a dual glucose/cholesterol meter application based on fpga platform is introduced. It consists of a dual glucose/cholesterol readout circuit, an analog to digital converter (ADC), a digital controller, a serial Electrically Erasable programmable Read-Only Memory (EEPROM), and a Liquid Crystal Display (LCD). The readout circuit is used to proportionally transfer the current signal detected by a glucose/cholesterol sensor. It was fabricated by 0.35 μm TSMC CMOS process with an area of 0.086 mm 2 and 409.29μW power consumption. The ADC is added to transfer the output signal of the readout chip in analog format to the input signal of the micro controller in the digital format. The digital controller is simulated by using a field programmable gate Array (fpga) as a platform, which displays the measured result on LCD and stores the detected data into the serial EEPROM. The linearity of this work is 0.9850 for the current sensing range of 5.01~22.3 μA within glucose concentration range of 50~400 mg/dL with the power consumption of this system is 46.893 mW and current sensing range of 500~600 μA within cholesterol concentration range of 150~300 mg/dL. In addition, this system can produce the glucose concentration (mg/dL) results within 11 seconds which is faster than current products and previous works [1], [2] and the cholesterol concentration (mg/dL) results within 20 seconds. Compared to previous systems, the experiment results show that this work has a better performance in terms of linearity, accuracy and power consumption.

关键词： Sugar Sensors Linearity field programmable gate arrays EPROM Power demand Current measurement

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Partitioning constraints and signal routing approach for multi-fpga prototyping platform

Partitioning constraints and signal routing approach for mul...

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IEEE international symposium on System-on-Chip

作者： Mariem Turki Habib Mehrez Zied Marrakchi Mohamed Abid LIP6 UPMC Paris FlexRAS Technologies Paris France CESlab Sfax Tunisia

With the global trend towards digital systems, designer's goal is to manage the system on chip complexity in accordance with the time to market constraint. Multi-fpga hardware prototyping is an important feature to validate the design before reaching the fabrication phase. However, since the design is partitioned into multi-fpga platform, the system frequency of the prototyped design is dramatically decreased due to the inter-fpga communications. In fact, the way in which the design is partitioned affects the number of inter-fpga signals and the critical path delay. In this paper, we propose a prototyping environment for multi-fpga platforms. The partitioner tool is constrained so that it tries to find the best trade off between criteria that affects the system frequency. The resulting inter-fpga signals are routed using an iterative routing algorithm. If the number of these signals exceeds the number of available traces between fpgas, multiplexing IPs are inserted in the sending and receiving fpga in order to transmit several signals through the same physical wire.

关键词： field programmable gate arrays Lead Hardware design languages Clocks Multiplexing Benchmark testing

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