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检索条件"任意字段=2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013"

共 809 条记录，以下是421-430 订阅

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Fault Tolerant CAN Bus Control System Implemented into fpga

Fault Tolerant CAN Bus Control System Implemented into FPGA

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IEEE international symposium on Design and Diagnostics of Electronic Circuits & Systems

作者： Karel Szurman Jan Kastil Martin Straka Zdenek Kotasek UNIS Brno University of Technology

ISBN: (纸本)9781467361354

For various types of applications, it is necessary to guarantee maximal level of fault tolerance and high reliability of components, avionic and railway applications can serve as an example of these applications. In these devices, electronic components are exhibited to the environment conditions, from among them especially cosmic radiation can have an undesired and destructive effect In this paper, the basic ideas of the design and implementation of CAN bus based control system into fpga platform is described. The bus control system uses CANAerospace application protocol. The fault tolerance features of the developed system are improved by TMR architecture. Then, experiments with SEU injection into the fpga configuration memory with both non-TMR and TMR architectures are described, the results presented and evaluated. In these experiments, SEU injection framework developed during our previous research was used which injects SEU failures into running fpga design.

关键词： Fault tolerance field programmable gate arrays Motor buses Single event upsets NUCLEOPORIN, 214-KD calcium ammonium nitrate RAILWAY APPLICATION Cosmic radiation tunneling magnetoresistance control systems

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A New System Interconnection Architecture Based on RapidIO Using Partial Reconfiguration

A New System Interconnection Architecture Based on RapidIO U...

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IEEE international symposium on Dependable, Autonomic and Secure Computing (DASC)

作者： Zhan Xu Xiao Wu Yi Wu School of Computer Science and Engineering NorthWestern Polytechnical University Xi'an China

Now in the field of embedded system, high-speed interconnection based on parallel or serial LVDS technology is becoming increasingly important. Because of this the first RapidIO offerings available in the market were fpga based, RapidIO interconnection had been identified as significant emerging technologies for fpgas to support. At the same time, as the fpgas increase in size, they are being large enough to accommodate both the static RapidIO interface and the reconfigurable logic. So, a consistent I/O interface is provided to support Reconfigurable Partition. This paper presents a new system interconnection architecture based on RapidIO to achieve the fpga run-time Reconfigurable Partition.

关键词： field programmable gate arrays Switches Program processors Clocks Registers Routing

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Routing algorithm for multi-fpga based systems using multi-point physical tracks

Routing algorithm for multi-FPGA based systems using multi-p...

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international Workshop on Rapid System Prototyping (RSP)

作者： Qingshan Tang Habib Mehrez Matthieu Tuna Laboratoire Informatique Paris-6 Université Pierre et Marie CURIE Paris France Flexras Technologies Paris France

Multi-fpga boards suffer from large timing delays in inter-fpga physical tracks compared to intra-fpga track delays, as well as a limited bandwidth between fpgas due to the limited number of I/Os per fpga. In order to tackle this problem, an algorithm which routes multi-terminal nets in multi-point tracks is proposed in this paper to spare fpga I/Os. Experiments are conducted using Gaisler Research Benchmarks. Firstly, each testbench will be implemented in an off-the-shelf board. The results show that the system frequency can be increased in the off-the-shelf board by the proposed routing algorithm. Secondly, an automatic design flow which generates a custom multi-fpga board is enhanced by generating multi-point tracks in the board, and each testbench will be implemented with the proposed routing algorithm in custom boards. The results show that the system frequency is improved in the custom board with both 2- and multi-point tracks.

关键词： field programmable gate arrays Routing Receivers Algorithm design and analysis Time division multiplexing Frequency division multiplexing

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A Comparison of Ruleset Feature Independent Packet Classification Engines on fpga

A Comparison of Ruleset Feature Independent Packet Classific...

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IEEE international symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Andrea Sanny Thilan Ganegedara Viktor K. Prasanna Ming Hsieh Dept. of Electrical Engineering University of Southern CA

ISBN: (纸本)9781479913725

Packet classification is used in network firewalls to identify and filter threats or unauthorized network access at the application level. This is realized by comparing incoming packet headers against a predefined rule set. Many solutions to packet classification are available, but most of these solutions exploit some features of the rule set in order to minimize the memory footprint of rule set storage. However, when the expected rule set features are not present, feature-reliant solutions may yield poor memory efficiency. In this paper, we focus on two rule set independent packet classification schemes, Ternary Content Addressable Memory (TCAM), a brute force search method, and StrideBV, a bit-vector-based algorithmic solution, to determine which solution is more suited for high performance packet classification. Using rule set sizes ranging from 32 to 2048 (targeted for firewall rule sets), we implement both schemes on a field-programmable gate Array (fpga) to evaluate their performance. We measure the performance using memory efficiency, resource consumption, throughput and power efficiency metrics for both solutions. The post place-and-route results on a state-of-the-art fpga reveal that StrideBV has 4.5× and 3.5× higher power efficiency in comparison with TCAM, along with 6× and 4× higher throughput when using distributed RAM and block RAM as memory respectively. TCAM has better memory efficiency, though its improvement over StrideBV varies.

关键词： Random access memory field programmable gate arrays Memory management Throughput IP networks Ports (Computers) Clocks

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Fine-Grained Manipulation of fpga Configuration for Incremental Design

Fine-Grained Manipulation of FPGA Configuration for Incremen...

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IEEE international symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Wenwei Zha Peter Athanas Bradley Department of Electrical and Computer Engineering Virginia Polytechnic Institute and State University Blacksburg VA

ISBN: (纸本)9781479913725

This paper presents the technique of manipulating fpga configuration in fine granularity to improve the efficiency of incremental design. The main contributions are achieving hardware autonomy and enhancing hardware development productivity, demonstrated by two categories of applications: implementing Autonomous Adaptive Systems and Fast System Progotyping. Vendor tools provide limited facilitation for these applications. For the first category, a system with a universal UART transmitter is demonstrated on the ML410 fpga board. The BAUD rate generating circuit is autonomously modified in hardware to adapt to the requirement of a remote UART receiver. For the second category, fast module assembly for prototyping a GNU Radio system is demonstrated on the XUPV5-LX110T fpga board. Its run-time is tens of times faster than that of the vendor tool. Moreover, to evaluate the quality of the proposed fine-grained manipulation, wire delay information is approximated through brute-force analysis. The delay estimation result achieves accuracy within 6% error as compared to that of the vendor tool's.

关键词： field programmable gate arrays Routing Hardware Delays Adaptive systems Communities Software

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Time delay digital beamforming for wideband pulsed radar implementation

Time delay digital beamforming for wideband pulsed radar imp...

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IEEE international symposium on Phased Array Systems and Technology

作者： Colman Cheung Ronak Shah Michael Parker Altera Corporation San Jose CA

Radar system has been using a hybrid of analog and digital beamforming. Sub-arrays of phase shifters in the analog domain are digitized at the sub-array outputs for further digital beamforming processing. Such system suffers from limited bandwidth and is unable to create more than one simultaneous beam. Digital time delay beamforming brings many benefits such as wide bandwidth pulse waveform and simultaneous beams at different angles, wave forms and frequencies. Such capabilities may have been deemed too expensive in the past, but is now within reach due to the high density of multipliers in the fpga and introduction of transceiver based ADC (Analog to Digital Converter)/ DAC (Digital to Analog Converter). This paper will present the design and implementation of a fractional delay (FD) filter used in time delay beamforming with Altera fpgas and tools. Other beamforming issues like wide bandwidth, adaptive beamforming and high density interconnect architectures for phased arrays will also be investigated.

关键词： Finite impulse response filters Array signal processing Delays Bandwidth field programmable gate arrays Filtering theory Delay effects

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A Multithreaded VLIW Soft Processor Family

A Multithreaded VLIW Soft Processor Family

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Annual IEEE symposium on field-programmable Custom Computing Machines (FCCM)

作者： Kalin Ovtcharov Ilian Tili J. Gregory Steffan Department of Electrical and Computer Engineering University of Toronto Canada

Summary form only given. There is growing commercial interest in using fpgas for compute acceleration. To ease the programming task for non-hardware-expert programmers, systems are emerging that can map high-level languages such as C and OpenCL to fpgas-targeting compiler-generated circuits and soft processing engines. Soft processing engines such as CPUs are familiar to programmers, can be reprogrammed quickly without rebuilding the fpga image, and by their general nature can support multiple software functions in a smaller area than the alternative of multiple per-function synthesized circuits. Finally, compelling processing engines can be incorporated into the output of high-level synthesis systems. For fpga-based soft compute engines to be compelling they must be computationally dense: they must achieve high throughput per area. For simple CPUs with simple functional units (FUs) it is relatively straightforward to achieve good utilization, and it is not overly-detrimental if a small, single-pipeline-stage FU such as an integer adder is under-utilized. In contrast, larger, more deeply pipelined, more numerous, and more varied FUs can be quite challenging to keep busy-even for an engine capable of extracting instruction-level parallelism (ILP) from an application. Hence a key challenge for fpga-based compute engines is how to maximize compute density (throughput per-area) by achieving high utilization of a datapath composed of multiple varying FUs of significant and varying pipeline depth. In this work, we propose a highly-parameterizable template architecture of a multi-threaded fpga-based compute engine designed to highly-utilize varied and deeply pipelined FUs. Our approach to achieving high utilization is to leverage (i) support for multiple thread contexts (ii) thread-level and instruction-level parallelism, and (iii) static compiler analysis and scheduling. We focus on deeply-pipelined, IEEE-754 floating-point FUs of widely-varying latency, executing both Ho

关键词： Engines Throughput field programmable gate arrays Instruction sets Area measurement Computer architecture Context

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Removal of measurement noise spikes in grid-connected power converters

Removal of measurement noise spikes in grid-connected power ...

引用

IEEE international symposium on Power Electronics for Distributed Generation Systems (PEDG)

作者： A. R. Haider Mohomad Christopher P Diduch Yevgen Biletskiy Riming Shao Liuchen Chang Department of Electrical and Computer Engineering University of New Brunswick Fredericton NB Canada

Power Electronic Converters (PECs) are routinely used to control the energy supplied to electric grids from distributed generators. The operation of PECs involves the control of voltage and current by rapidly switching power semiconductor devices. Rapid switching of these devices causes a certain class of high frequency noise called spikes which in turn are induced into sensor measurements. In addition to PEC control functions, the sensor measurements are also used to detect over current (OI) over voltage (OV) and under voltage (UV) faults. The presence of noise spikes compromises the performance and leads to unnecessary triggering of fault protection circuitry as a result of false detection of over/under voltage and current faults. The development of a new algorithm to remove short time electrical spikes from PEC sensors is the focus of this paper. In such a way, the PEC is unaffected and false OI, OV, and UV alarms are eliminated. The methodology uses the discrete wavelet transform (DWT) to generate a feature space where the spike feature is detected and removed, and the inverse DWT to reconstruct spike-free measurements. A field-programmable gate Array (fpga)-based interface board is designed to implement the new algorithm within an actual PEC system. The designed fpga board along with the new algorithm is used in integration of distributed generators into power systems.

关键词： Discrete wavelet transforms Filter banks Current measurement field programmable gate arrays Noise Finite impulse response filters

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fpga-based HPC application design for non-experts

FPGA-based HPC application design for non-experts

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international Workshop on Rapid System Prototyping (RSP)

作者： David Uliana Krzysztof Kepa Peter Athanas Virginia Polytechnic Institute and State University Blacksburg VA USA

In the current era of big-data computing, most non-engineer domain experts lack the skills needed to design fpga-based hardware accelerators to address big-data problems in their fields. This work presents bFlow, a development environment that facilitates the assembly of such accelerators, specifically those targeting fpga-based hybrid computing platforms, such as the Convey HC series. This framework attempts to address the above problem by making use of an abstracted, graphical front-end more friendly to users without computer engineering backgrounds than traditional, HDL-based design environments, as well as by accelerating bitstream compilation by means of incremental implementation techniques. bFlow's performance, usability, and application to big-data life-science problems were tested by participants of an NSF-funded Summer Institute organized by the Virginia Bioinformatics Institute (VBI). In about one week, a group of four non-engineering participants made significant improvements to a reference Smith-Waterman implementation, adding functionality and scaling theoretical throughput by a factor of 32.

关键词： Computer architecture Hardware design languages Hardware Servers field programmable gate arrays Algorithm design and analysis Software

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RSD based Karatsuba multiplier for ECC processors

RSD based Karatsuba multiplier for ECC processors

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international Design and Test Workshop

作者： H. Marzouqi M. Al-Qutayri K. Salah Department of Electrical and Computer Engineering Khalifa University UAE

This paper proposes a 256 Redundant Signed Digits hardware multiplier based on Karatsuba that is suitable for prime field ECC processors. Redundant representation is essential for prime field ECC processors as the basis for carry free arithmetic. The proposed multiplier works by applying Karatsuba method at two levels where three recursively constructed blocks are used to perform large integer multiplication iteratively. Different design alternatives are presented and implemented in Xilinx Virtex-5 fpga. A pipelined multiplier with a recursive blocks of size 64 digits can perform one full 256 RSD digits multiplication within 1.08μs, operating at maximum frequency of 61.91 MHz.

关键词： Hardware Program processors Complexity theory Clocks Educational institutions field programmable gate arrays Delays

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