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检索条件"任意字段=2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013"

共 809 条记录，以下是431-440 订阅

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Current slope calculation in fpga for sensorless control technique and associated slope based predictive precise current control

Current slope calculation in FPGA for sensorless control tec...

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Sensorless Control for Electrical Drives (SLED)

作者： Jinou Wang Andreas Binder Institute of Electrical Energy Conversion Technische Universität Darmstadt Darmstadt Germany

This paper introduces a new approach to measure the current slope only with normal current sensors. The current slope, which is caused by voltage switching of PWM amplifiers, can be used for a sensorless control technique for magnetic bearings or electrical drives. Further, with the information of the slope, we can realize a predictive precise current control. By combining the current sensor, analogue-to-digital converter and fpga, using the proposed multiple current sampling technique, the current slope will be calculated in hardware with the method of least squares. This sub-system acts like a virtual sensor, which delivers both current and its slope values at the given sample point.

关键词： Sensors Current control Pulse width modulation field programmable gate arrays Current measurement Magnetic levitation Coils

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Fast fpga-based fault injection tool for embedded processors

Fast FPGA-based fault injection tool for embedded processors

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IEEE international symposium on Quality Electronic Design

作者： Mohammad Shokrolah Shirazi Brendan Morris Henry Selvaraj Department of Electrical and Computer Engineering University of Nevada Las Vegas USA

fpga-based fault injection methods have recently become more popular since they provide high speed in fault injection experiments. During each fault injection experiment, fpga should send data related with observation points back to host computer for fault tolerant analysis. Since there is high data volume, fpga should spend most of its time in communication. In this paper, we solve this problem by bringing all parts of fault injection tool inside fpga. The area overhead problem related with observation data is obviated by using simple observation circuit. As case study, we injected 6400 SEU faults into OpensRISC 1200 processor over the Cyclone II fpga. Results show that our fault injection experiments are done more than 400 times faster than one of the traditional fpga based fault injection methods with only 5% area overhead.

关键词： Circuit faults field programmable gate arrays Program processors Computers Instruments Clocks Hardware

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A Classification Processor for a Support Vector Machine with Embedded DSP Slices and Block RAMs in the fpga

A Classification Processor for a Support Vector Machine with...

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IEEE international symposium on Embedded Multicore Socs (MCSoC)

作者： Yuki Ago Koji Nakano Yasuaki Ito Department of Information Engineering Hiroshima University Higashi-Hiroshima JAPAN

This paper presents an fpga implementation of a Support Vector Machine (SVM) classification using the DSP slices and block RAMs in the Xilinx Virtex-6 family fpga. In our approach, the SVM classification is performed by the multiple DSPs. Our implementation supports 3 types of kernel functions, the sigmoid kernel, the polynomial kernel, and the RBF kernel. We connect DSPs with the built-in cascade logic in a DSP slice. Thus, our architecture consists of a cascaded DSP pipeline and process the input data with this pipeline. The number of DSP slices included in this cascade connection is equal to the number of the support vectors in the SVM. We have implemented the processor core which includes 768 DSPs for SVM classification in a Xilinx Virtex-6 fpga XC6VLX240T-FF1156. The implementation results show that it can be implemented in the fpga with 768 DSP48E1 slices, 800 block RAMs and 17680 slices. It runs in 370.096MHz clock frequency and can evaluate the SVM classification for 128-dimensional feature space data 2.89×10 6 times per second.

关键词： Support vector machines Kernel Digital signal processing Random access memory field programmable gate arrays Computer architecture Vectors

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Low Complexity fpga Implementation of Emotion Detection for Autistic Children

Low Complexity FPGA Implementation of Emotion Detection for ...

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international symposium on Medical Information & Communication Technology (ISMICT)

作者： K. G. Smitha A. P. Vinod School of Computer Engineering Nanyang Technological University Singapore

Many autistic children have impairment in understanding other people's emotions which hinder their interpersonal communication. A real-time portable emotion detection system will aid such children to interact with the external world easily by them to understand facial emotions during their face to face communication. In this paper we propose a portable low complexity emotion detector using principal component analysis. The Eigen values are obtained using power-deflation iteration method and the proposed architecture optimizes the calculation by using only the required number of selective Eigen values called as Eigen range rather than finding all the Eigen values and vectors. The proposed emotion recognizer architecture is implemented on Virtex 7 XC7VX330T FFG1761-3 fpga. We achieved 82.3 % detection accuracy for a wordlength of 8 bits.

关键词： Emotion recognition Accuracy Feature extraction Principal component analysis Vectors Hardware field programmable gate arrays

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SW and HW speculative Nelder-Mead execution for high performance unconstrained optimization

SW and HW speculative Nelder-Mead execution for high perform...

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IEEE international symposium on System-on-Chip

作者： Artur Mariano Paulo Garcia Tiago Gomes Institute for Scientific Computing Technische Universität Darmstadt Darmstadt Germany Centro Algoritmi Universidade do Minho Guimarães Portugal

This paper addresses the performance assessment of a new Nelder-Mead variant, that speculatively executes the simplex operations. This new variant was implemented as x86 parallel and sequential CPU versions as well as in handwritten and automatic C-to-RTL fpga designs. As the execution flow is the same on every version, the efficiency of the synchronization by software and hardware is also accessed. Performance trials of these versions where performed using (i) a last-generation fpga and a last generation multi-core CPU-chip to run the software versions and (ii) relatively simple objective functions in ℝ 2 . Results show that performance of the handwritten hardware design is relatively equivalent to the sequential software version of the algorithm, even running at a much lower clock frequency (average of 1.9Mhz vs 3.4GHz). They also suggest that the synchronization methods employed to control the speculative execution are too expensive when managed by software, but efficient if managed by hardware.

关键词： Digital signal processing Synchronization Registers Table lookup Reflection Clocks field programmable gate arrays

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Heterogeneous CPU/fpga Reconfigurable Computing System for Avionic Test Application

Heterogeneous CPU/FPGA Reconfigurable Computing System for A...

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IEEE international symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： George Afonso Zeineb Baklouti David Duvivier Rabie Ben Atitallah Eli Billauer Stephan Stilkerich EADS IW INRIA Lille Nord Europe LAMIH University of Valenciennes Xillybus company EADS IW Germany

ISBN: (纸本)9781479913725

Real-time computing systems are increasingly used in aerospace and avionic industries. In the face of power wall and real-time requirements, hardware designers are directed towards reconfigurable computing with the usage of heterogeneous CPU/fpga systems. However, there is a lack of real-time environments able to deal with the execution of applications on such heterogeneous systems dedicated to avionic Test and Simulation (T&S). This research investigates the problem of soft real-time environments for CPU/fpga systems and proposes first a high-performance hardware architecture used to implement intimately coupled hardware and software avionic models. Second, this paper presents the description of an efficient real-time software environment for the model's execution, the multi-core CPU monitoring and the runtime task re-allocation to avoid the timing constraint violation. Experimental results underpin the industrial relevance of the presented approach for avionic T&S systems with real-time support.

关键词： field programmable gate arrays Real-time systems Hardware Aerospace electronics Computer architecture Software Adaptation models

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Efficient distributed memory management in a multi-core H.264 decoder on fpga

Efficient distributed memory management in a multi-core H.26...

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IEEE international symposium on System-on-Chip

作者： Jiajie Zhang Zheng Yu Zhiyi Yu Kexin Zhang Zhonghai Lu Axel Jantsch State Key Lab of ASIC and System Fudan University Shanghai China Memcom. Soc Microelectronics co. ltd Wuxi China KTH-Royal Institute of Technology Kista Sweden

Memory management is a challenging issue of multi-core architecture. With growing core numbers, Distributed Shared Memory (DSM) is becoming a general trend. In this paper, a DSM based multi-core architecture is explored and evaluated via an H.264 decoder application. The memory access and communication over Network-on-Chips is managed by the Data Management Engine (DME). Experimental results realized on an Altera Stratix VI show that 9-node distributed memory system increases performance by 1.5x compared to centralized memory. Moreover, the performance of proposed DSM architecture grows linearly with the number of cores deployed.

关键词： Delays Entropy Decoding field programmable gate arrays

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fpga-based smart-sensor for fault detection in VSD-fed induction motors

FPGA-based smart-sensor for fault detection in VSD-fed induc...

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IEEE international symposium on Diagnostics for Electric Machines, Power Electronics and Drives (SDEMPED)

作者： A. G. Garcia-Ramirez R. A. Osornio-Rios A. Garcia-Perez Rene de Jesus Romero-Troncoso HSPdigital CA-Mecatronica at Facultad de Ingenieria Campus San Juan del Rio Universidad Autonoma de Queretaro San Juan del Rio Queretaro Mexico HSPdigital CA-Telematica at DICIS University of Guanajuato Salamanca Mexico HSPdigital CA-Mecatronica at Facultad de Ingenieria Universidad Autonoma de Queretaro Qro Mexico HSPdigital CA-Procesamiento Digital de Señales at DICIS University of Guanajuato Salamanca Guanajuato Mexico HSPdigital CA-Telematica at DICIS Universidad de Guanajuato Guanajuato Guanajuato MX

Nowadays, different industrial processes use induction motors fed through variable speed drives (VSD). In order to improve these processes, the industry demands the use of smart sensors to detect the faults, reduce the cost of maintenance, and decrease power consumption. In this work, broken rotor bars, unbalance and misalignment are automatically detected in induction motors fed by a VSD using the three current phases online, with a smart sensor. The proposed smart sensor is implemented in a field programmable gate array offering a low computational load methodology, low- cost, and portable solution for fault detection in induction motors VSD-fed. Results show a high effectiveness detection of the treated faults.

关键词： Induction motors Intelligent sensors Artificial neural networks Rotors Transforms field programmable gate arrays Bars

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Implementation of power transmission lines to field programmable gate array ICs for managing signal and power integrity

Implementation of power transmission lines to field programm...

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IEEE international symposium on Electromagnetic Compatibility (EMC)

作者： Sang Kyu Kim Satyanarayana Telikepalli Sung Joo Park Madhavan Swaminathan David Keezer Youkeun Han Department of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA Department of Electrical and Computer Engineering Georgia Institute of Technology 266 Ferst Dr. Atlanta 30328 USA Memory Division Samsung Electronics Co. Ltd Hwasung-city Gyeonggi-do Korea

ISBN: (纸本)9781479904112

As the operating frequencies of electronic devices increase, power and signal integrity have become a major issue. Simultaneous switching noise (SSN) is a major problem that restricts the performance of high speed digital systems. SSN leads to voltage fluctuations during data transitions which can induce excessive noise. SSN is caused by parasitic inductance components in the power delivery network (PDN) that manifest themselves through via transitions, apertures on reference plane, split planes and even solid planes. A new method has been proposed to address this problem, which employs power transmission lines (PTL) that supply power to integrated circuits instead of using the conventional power/ground plane pairs. This along with current balancing can be used to manage return path discontinuities and power supply noise. Many of the published work in this area have proved that the PTL concept is able to reduce SSN and enhance power and signal integrity. Pseudo-balanced power transmission line (PB-PTL) concept has been shown to improve performance and reduce power consumption. However, this has only been applied to relatively simple test vehicles. In this paper, the PB-PTL scheme has been extended for driving multiple I/O drivers in field programmable gate array (fpga) ICs. This paper discusses the theory, simulation and measurement results for this implementation.

关键词： Encoding Vehicles Power transmission lines field programmable gate arrays Power supplies Resistors Jitter

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High-Level Description and Synthesis of Floating-Point Accumulators on fpga

High-Level Description and Synthesis of Floating-Point Accum...

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Annual IEEE symposium on field-programmable Custom Computing Machines (FCCM)

作者： Marc-Andre Daigneault Jean Pierre David Departement of Electrical Engineering Ecole Polytechnique de Montreal Montreal Canada

Decades of research in the field of high level hardware description now result in tools that are able to automatically transform C/C++ constructs into highly optimized parallel and pipelined architectures. Such approaches work fine when the control flow is a priory known since the computation results in a large dataflow graph that can be mapped into the available operators. Nevertheless, some applications have a control flow that is highly dependant on the data. This paper focuses on the hardware implementation of such applications and presents a high level synthesis methodology applied to a Hardware Description Language (HDL) in which assignments correspond to self-synchronized connections between predefined data streaming sources and sinks. A data transfer occurs over an established connection when both source and sink are ready, according to their synchronization interfaces. Founded on a high-level communicating FSM programming model, the language allows the user to describe and dynamically modify streaming architectures exploiting spatial and temporal parallelism. Our compiler attempts to maximize the number of transfers at each clock cycle and automatically fixes the potential combinatorial loops induced by the dynamic connection of dependant sources and sinks. The methodology is applied to the synthesis of a pipelined floating point accumulator using the Delayed-Buffering (DB) reduction method. The results we obtain are similar to state-of-the-art dedicated architectures but require much less design time and expertise.

关键词： Synchronization Hardware Data transfer Adders Hardware design languages Computer architecture field programmable gate arrays

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