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检索条件"任意字段=2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013"

共 809 条记录，以下是441-450 订阅

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A Fast Discrete Placement Algorithm for fpgas 12

A Fast Discrete Placement Algorithm for FPGAs

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20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Wu, Qinghong McElvain, Kenneth S. Synopsys Inc Mountain View CA 94043 USA

ISBN: (纸本)9781450311557

Good fpga placement is crucial to obtain the best Quality of Results (QoR) from fpga hardware. Although many published global placement techniques place objects in a continuous ASIC-like environment, fpgas are discrete in nature, and a continuous algorithm cannot always achieve superior QoR by itself. Therefore, discrete fpga-specific detail placement algorithms are used to improve the global placement results. Unfortunately, most of these detail placement algorithms do not have a global view. This paper presents a discrete "middle" placer that fills the gap between the two placement steps. It works like simulated annealing, but leverages various acceleration techniques. It does not pay the runtime penalty typical of simulated annealing solutions. Experiments show that with this placer, final QoR is significantly better than with the global-detail placer approach.

关键词： Computer-aided design (CAD) individual cell temperature window masking dynamic window field-programmable gate array (fpga) placement simulated annealing

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Assertion Based Verification Using PSL-like Properties In Haskell

Assertion Based Verification Using PSL-like Properties In Ha...

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IEEE international symposium on Design and Diagnostics of Electronic Circuits & Systems

作者： B. N. Uchevler Kjetil Svarstad Norwegian University of Science and Technology

ISBN: (纸本)9781467361354

With the increasing complexity of designs, the verification costs grow considerably. Using Assertion Based Verification with assertions implemented on real hardware, can speed up the verification process. Property Specification Language is one of the common standards for describing formal properties and specifications of a design. We implemented a subset of PSL operations in Haskell in this work. A functional programming language like Haskell can appear as an advantageous choice for formal verification and high-level descriptions. We use the implemented PSL operators to set up different synthesizable PSL properties. The implemented PSL operators are tested on an fpga for an AMBA AHB-based system which is also implemented in Haskell.

关键词： Functional programming Verification Formal verification Specifications field programmable gate arrays functional programming language

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An fpga-Based Data Flow Engine for Gaussian Copula Model

An FPGA-Based Data Flow Engine for Gaussian Copula Model

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Annual IEEE symposium on field-programmable Custom Computing Machines (FCCM)

作者： Huabin Ruan Xiaomeng Huang Haohuan Fu Guangwen Yang Wayne Luk Sebastien Racaniere Oliver Pell Wenjing Han Department of Computer Science and Technology Tsinghua University Beijing China Center for Earth System Science Tsinghua University Beijing China Department of Computer Engineering Imperial College London London UK Maxeler Technologies London UK School of Computer Science and Technology Harbin Institute of Technology Harbin China

The Gaussian Copula Model (GCM) plays an important role in the state-of-the-art financial analysis field for modeling the dependence of financial assets. However, the existing implementations of GCM are all computationallydemanding and time-consuming. In this paper, we propose a Dataflow Engine (DFE) design to accelerate the GCM computation. Specifically, a commonly used CPU-friendly GCM algorithm is converted into a fully-pipelined dataflow graph through four steps of optimization: recomposing the algorithm to be pipeline-friendly, removing unnecessary computation, sharing common computing results, and reducing the computing precision while maintaining the same level of accuracy for the computation results. The performance of the proposed DFE design is compared with three CPU-based implementations that are well-optimized. Experimental results show that our DFE solution not only generates fairly accurate result, but also achieves a maximum of 467x speedup over a single-thread CPU-based solution, 120x speedup over a multi-thread CPUbased solution, and 47x speedup over an MPI-based solution.

关键词： field programmable gate arrays Computer architecture Computational modeling Optimization Hardware Pipelines Algorithm design and analysis

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MAMPSx: A design framework for rapid synthesis of predictable heterogeneous MPSoCs

MAMPSx: A design framework for rapid synthesis of predictabl...

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international Workshop on Rapid System Prototyping (RSP)

作者： Shakith Fernando Firew Siyoum Yifan He Akash Kumar Henk Corporaal Department of Electrical Engineering Eindhoven University of Technology The Netherlands Department of Electrical & Computer Engineering National University of Singapore Singapore

Heterogeneous Multiprocessor System-on-Chips (HMPSoC) are becoming popular as a means of meeting energy efficiency requirements of modern embedded systems. However, as these HMPSoCs run multimedia applications as well, they also need to meet real-time requirements. Designing these predictable HMPSoCs is a key challenge, as the current design methods for these platforms are either semi-automated, non-predictable, or have limited heterogeneity. In this paper, we propose a design framework to generate and program HMPSoC designs in a rapid and predictable manner. It takes the application specifications and the architecture model as input and generates the entire HMPSoC, for fpga prototyping, that meets the throughput constraints. The experimental results show that our framework can provide a conservative bound on the worst-case throughput of the fpga implementation. We also present results of a case study that computes the area-power trade-offs of an industrial vision application. The entire design space exploration of all configurations was completed in 8 hours. A tool-chain targeting the Xilinx Zynq fpga is also presented.

关键词： Tiles Computational modeling Computer architecture Analytical models field programmable gate arrays Nickel Predictive models

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Defect recovery in nanodevice-based programmable interconnects (abstract only) 13

Defect recovery in nanodevice-based programmable interconnec...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Jason Cong Bingjun Xiao UCLA Los Angeles CA USA

ISBN: (纸本)9781450318877

This work focuses on defect tolerance for nanodevice-based programmable interconnects of fpgas. A single nanodevice can function as a routing switch in place of a pass transistor and its six-transistor SRAM cell in conventional fpgas. Defects of nanodevices in programmable interconnects are manifested as losses of configurability and can be categorized into stuck- open defect and stuck- closed defect. First, we show that the stuck-closed defects of nanodevices have a much higher impact than the stuck-open defects. Instead of simply avoiding the stuck-closed defects, we recover them by treating them as shorting constraints in the routing. We develop a scalable algorithm to perform timing-driven routing under these extra constraints. We extend the idea of the resource negotiation to balance the goals of timing and routability under shorting constraints. We also develop several techniques to guide the router to map the shorting clusters to those nets with more shared paths for better utilization of routing resources while automatically balancing it with circuit performance. We also enhance the placement algorithm to recover logic blocks which become virtually unusable due to shorted pins. Simulation results show that at the up-to-date level of nanodevice defects (108-1011x higher than CMOS), compared to the simple avoidance method, our approach reduces the degradation of resource usage by 87%, improves the routability by 37%, and reduce the degradation of circuit performance by 36%, at a negligible overhead of tool runtime.

关键词： nanodevice defect tolerance route programmable interconnects placement

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A CAM-based Information Detection Hardware System for Fast Exact Pattern Matching

A CAM-based Information Detection Hardware System for Fast E...

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IEEE international Midwest symposium on Circuits and Systems

作者： Duc-Hung Le Tran-Bao-Thuong Cao Katsumi Inoue Cong-Kha Pham The University of Electro-Communications The University of Science Ho Chi Minh City Advanced Original Technologies

ISBN: (纸本)9781479900657

A CAM-based Information Detection Hardware System for fast exact pattern matching is implemented on a hardware system with fpga and ASIC. The system has a simple structure, does not employ any Central Processor Unit (CPU) as well as complicated algorithms. We take advantage of Content Addressable Memory (CAM) which has an ability of parallel multi-match mode for designing the system. The system is applied to fast pattern matching with various required search patterns without using any search principles. In this paper, the authors present the system for exact pattern matching on 2-D data.

关键词： fpga ASIC Information Detection Hardware System Content Addressable Memory (CAM) Multi-match Exact pattern matching Pattern matching ASIC application specific integrated circuits field programmable gate arrays Hardware system Fasting simple structures Exact

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Cipher-destroying and secret-key-emitting hardware Trojan against AES core

Cipher-destroying and secret-key-emitting hardware Trojan ag...

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Midwest symposium on Circuits and Systems (MWSCAS)

作者： Takeshi Kumaki Masaya Yoshikawa Takeshi Fujino Dept. of Science and Engineering Ritsumeikan University Japan Dept. of Information Engineering Meijo University Japan

This paper reports cipher-destroying and secret-key-emitting hardware Trojan against Advanced Encryption Standard (AES) cores in order to facilitate countermeasures against such Trojans. We developed a malicious circuit that connects the encryption and decryption modules in the AES core. If an attacker-defined predetermined rule is satisfied in the AES core, the hardware Trojan is triggered and it sends half-encoded data from the encryption module to the decryption module via a Trojan path. As a result, plain text is directly delivered to the output port. Furthermore, if the hardware Trojan-inserted AES core is inputted with a predefined keyword, which is transferred to a controller via the Trojan path, a secret-key is directly outputted. To verify the threat of AES hardware Trojan, we evaluated the field programmable gate Array (fpga) and Application Specific Integrated Circuit (ASIC) implementation results from the Verilog-Hardware Description Language (HDL) macro. From the fpga implementation of a conventional AES core and malicious AES core on the microblaze system, additional hardware of the malicious circuit was about 0.18% larger than the normal AES core. The maximum operating frequency of the malicious AES core was the same as that of the normal one. From the ASIC implementation, additional hardware and power consumption of the malicious circuit was about 0.37% and 0.13% larger than the normal one, respectively. Therefore, we argue that the development of hardware Trojan analysis and detection techniques must be accelerated for ensuring the reliability of LSI products.

关键词： Hardware Trojan horses Encryption Large scale integration Ciphers field programmable gate arrays Application specific integrated circuits

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Hardware-Software Codesign of EKF-Based Motor Control for Domain-Specific Reconfigurable Platform

Hardware-Software Codesign of EKF-Based Motor Control for Do...

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international symposium on Electronic System Design (ISED)

作者： Yan Lin Aung Siew-Kei Lam Thambipillai Srikanthan CHiPES Research Centre Nanyang Technological University Singapore

This paper presents hardware-software code sign of Extended Kalman Filter (EKF) based motor control for a domain specific reconfigurable platform, which consists of a processor for automotive applications and an fpga for application specific customization. Considering the existing MISRA C compliant software harnessing dedicated on chip peripherals, we employ a code sign methodology aiming to enable product differentiation through modest hardware accelerator implementation in the reconfigurable logic thus meeting the application constraints under tight time to market pressure. A key step in the design methodology for reducing the effort of hardware customization lies in platform-aware hardware-software partitioning, which takes into accounts communication overhead between the various computing elements. We show that our approach can effectively identify a suitable candidate for hardware acceleration embracing domain specific characteristics and existing standard compliant software.

关键词： field programmable gate arrays Kalman filters Hardware Software Motor drives Algorithm design and analysis Acceleration

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High radix montgomery modular multiplication on fpga

High radix montgomery modular multiplication on FPGA

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international Design and Test Workshop

作者： Anane Mohamed Anane Nadjia ESI (Ecole nationale Supérieure d'Informatique) Alger Algérie CDTA (Centre de Développement des Technologies Avancées)

Enhancing Montgomery modular multiplication (MMM) performances in term of speed and area is crucial for public key cryptography applications. This paper presents an efficient hardware-algorithm for a high radix MMM method that exploits the features available in the Virtex-5 Xilinx fpga. Our main contribution in this paper is to develop hardware algorithms for radix-2 16 number system in the fpga to speed up the MMM. It performs an operation of two 1024-bits numbers on 64 iterations. The CS (Carry Save) representation is advantageously used to overcome the carry propagation then the iteration cycle datapath length independent. Specials efforts were made to design, at the LUT level, the compressor 6:2, which is the key feature of our design. The resulting architecture can run with clock period equivalent to the total delay of an embedded 18×18-bits and two LUT6.

关键词： field programmable gate arrays Computer architecture Delays Hardware Public key cryptography Clocks Algorithm design and analysis

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Reducing the Cost of Floating-Point Mantissa Alignment and Normalization in fpgas 12

Reducing the Cost of Floating-Point Mantissa Alignment and N...

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20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Moctar, Yehdhih Ould Mohammed George, Nithin Parandeh-Afshar, Hadi Ienne, Paolo Lemieux, Guy G. F. Brisk, Philip Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA

ISBN: (纸本)9781450311557

In floating-point datapaths synthesized on fpgas, the shifters that perform mantissa alignment and normalization consume a disproportionate number of LUTs. Shifters are implemented using several rows of small multiplexers;unfortunately, multiplexer-based logic structures map poorly onto LUTs. fpgas, meanwhile, contain a large number of multiplexers in the programmable routing network;these multiplexer are placed under static control of the fpga's configuration bitstream. In this work, we modify some of the routing multiplexers in the intra-cluster routing network of a CLB in an fpga to implement shifters for floating-point mantissa alignment and normalization;the number of CLBs required for these operations is reduced by 67%. If shifting is not required, the routing multiplexers that have been modified can be configured to operate as normal routing multiplexers, so no functionality is sacrificed. The area overhead incurred by these modifications is small, and there is no need to modify every routing multiplexer in the fpga. Experiments show that there is no negative impact in terms of clock frequency or routability for benchmarks that do not use the dynamic multiplexers.

关键词： field programmable gate Array (fpga) Floating-point Mantissa Alignment Normalization

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