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检索条件"任意字段=2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013"

共 809 条记录，以下是471-480 订阅

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Intra-Masking Dual-Rail Memory on LUT Implementation for Tamper-Resistant AES on fpga 12

Intra-Masking Dual-Rail Memory on LUT Implementation for Tam...

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20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Hoang, Anh-Tuan Fujino, Takeshi Ritsumeikan Univ Kusatsu Shiga 5258577 Japan

ISBN: (纸本)9781450311557

In current countermeasure design trends against differential power analysis (DPA), security at gate level is required in addition to the security algorithm. Several dual-rail pre-charge logics (DPL) have been proposed to achieve this goal. Designs using ASIC can attain this goal owing to its backend design restrictions on placement and routing. However, implementing these designs on field programmable gate arrays (fpga) without information leakage is still a problem because of the difficulty involved in the restrictions on placement and routing on fpga. This paper describes our novel masked dual-rail pre-charged memory approach, called "intra-masking dual-rail memory on LUT," and its implementation on fpga for tamper-resistant AES. In the proposed design, all unsafe nodes, such as unmasking and masking, and the dual-rail memory and buses are packed into a single LUT. This makes them balanced and independent of the placement and routing tools. The design is independent of the cryptographic algorithm, and hence, it can be applied to available cryptographic standards such as DES or AES as well as future standards. It requires no special placement or route constraints in its implementation. A correlation power analysis (CPA) attack on 1,000,000 traces of AES implementation on fpga showed that the secret information is well protected against first-order side-channel attacks. Even though the number of LUTs used for memory in this implementation is seven times greater than that of the conventional unprotected single-rail memory table-lookup AES and three times greater than the implementation based on a composite field, it requires a smaller number of LUTs than all other advanced tamper-resistant implementations such as the wave dynamic differential logic, masked dual-rail pre-charge logic, and threshold.

关键词： Side-Channel Attack Differential Power Analysis (DPA) Masking Dual-Rail Memory Intra-Masking Dual-Rail Memory on LUT Tamper Resistance AES field programmable gate Array (fpga)

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Impact of fpga architecture on resource sharing in high-level synthesis 12

Impact of FPGA architecture on resource sharing in high-leve...

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2012 acm/sigda international symposium on field programmable gate arrays, fpga'12

作者： Hadjis, Stefan Canis, Andrew Anderson, Jason H. Choi, Jongsok Nam, Kevin Brown, Stephen Czajkowski, Tomasz ECE Department University of Toronto Toronto ON Canada Altera Toronto Technology Centre Toronto ON Canada

ISBN: (纸本)9781450311557

Resource sharing is a key area-reduction approach in high-level synthesis (HLS) in which a single hardware functional unit is used to implement multiple operations in the high-level circuit specification. We show that the utility of sharing depends on the underlying fpga logic element architecture and that different sharing trade-offs exist when 4-LUTs vs. 6-LUTs are used. We further show that certain multi-operator patterns occur multiple times in programs, creating additional opportunities for sharing larger composite functional units comprised of patterns of interconnected operators. A sharing cost/benefit analysis is used to inform decisions made in the binding phase of an HLS tool, whose RTL output is targeted to Altera commercial fpga families: Stratix IV (dual-output 6-LUTs) and Cyclone II (4-LUTs). © 2012 acm.

关键词： field programmable gate arrays (fpga)

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A low cost embedded real time 3D stereo matching system for surveillance applications

A low cost embedded real time 3D stereo matching system for ...

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IEEE symposium on Bioinformatics and Bioengineering (BIBE)

作者： Georgia Rematska Kyprianos Papadimitriou Apostolos Dollas TUC School of Electronic and Computer Engineering Chania Greece

The implementation of low-cost 3D Stereo Vision systems requires stereo matching algorithms. Various efforts have been reported in the literature, however, these systems require substantial hardware resources. The contribution of the present work is on a low-cost real-time system, which was fully implemented on a small Xilinx fpga. The system presented in this work extends previous results of the authors through design space exploration, architecture improvements and careful problem sizing.

关键词： Stereo vision field programmable gate arrays Cameras Image resolution Resource management Table lookup

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Towards a Certifiable Integration of SRAM-Based fpgas in Safety-Critical Automotive Systems

Towards a Certifiable Integration of SRAM-Based FPGAs in Saf...

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Pacific Rim international symposium on Dependable Computing

作者： Henning Sahlbach Rolf Ernst Institute of Computer and Network Engineering Technische Universität Braunschweig Germany

Advanced interconnected electronic systems play crucial roles in recent vehicle generations and have resulted in a significant increase of mileage and the introduction of several novel automotive features. For complex driver assistance applications, fpgas have started to replace established embedded or signal processors, providing high-performance processing capabilities at modest energy consumption. However, their certification in safety-critical applications is a challenging task, which is due to their internal configuration memory-based computer architecture, requiring adapted analysis and error mitigation approaches. Using a recommended automotive safety analysis technique, this paper evaluates a generic in-vehicle fpga-based computer platform regarding its certification limitations in automotive context. A suitable configuration memory safety concept for applications with highest safety integrity levels is then developed by combining established error mitigation mechanisms, which are also evaluated experimentally on an automotive prototyping platform. The obtained concept supports the execution of safety-critical applications on reconfigurable logic and proposes a viable certification path for automotive fpgas considering recent safety standards.

关键词： field programmable gate arrays Automotive engineering Random access memory Safety Vehicles Context Computer architecture

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Design of the DC leakage current sensor with magnetic modulation-based scheme

Design of the DC leakage current sensor with magnetic modula...

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IEEE international symposium on Industrial Electronics (ISIE)

作者： Cheng-Fa Cheng Rong-Sing Li Jyue-Ru Chen Department of Communications Navigation and Control Engineering National Taiwan Ocean University Taiwan

ISBN: (纸本)9781467351942

Currently, the DC leakage current sensor is mainly used in the MRT DC substation to prevent cable insulation failure and monitor security on each DC cable leakage current to ensure the quality of power supplies. In this paper, the magnetic modulation DC leakage current sensor with rapid demagnetization will be investigated. In terms of circuit design, the signal originates from a square wave generator and is then sent to a third-order low-pass filter for signal demodulation. The modulated signals pass through the offset compensation circuit and will be integrated to achieve the balance of the core flux. The characteristics of the system will be analyzed with the aids of the core magnetization curve and the sensing circuit measurements of the micro-current, rated current and high current response. fpga-based platform will also be employed to design the demagnetization and calibration control circuits such that the automatic DC leakage current monitoring system can be implemented. Finally, the proposed DC leakage sensing system will be simulated by the tool Multisim to validate the accuracy of the measurement system and verify the functions of the design requirements.

关键词： Demagnetization Magnetic cores Coils Current measurement Magnetic flux Leakage currents field programmable gate arrays

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Wire-Speed Implementation of Sliding-Window Aggregate Operator over Out-of-Order Data Streams

Wire-Speed Implementation of Sliding-Window Aggregate Operat...

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IEEE international symposium on Embedded Multicore Socs (MCSoC)

作者： Yasin Oge Masato Yoshimi Takefumi Miyoshi Hideyuki Kawashima Hidetsugu Irie Tsutomu Yoshinaga Graduate School of Information Systems The University of Electro-Communications Japan Tokyo Japan e-trees.Japan Inc. Tokyo University of Tsukuba Japan Tsukuba Ibaraki Japan

This paper shows the design and evaluation of an fpga-based accelerator for sliding-window aggregation over data streams with out-of-order data arrival. We propose an order-agnostic hardware implementation technique for windowing operators based on a one-pass query evaluation strategy called Window-ID, which is originally proposed for software implementation. The proposed implementation succeeds to process out-of-order data items, or tuples, at wire speed due to the simultaneous evaluations of overlapping sliding-windows. In order to verify the effectiveness of the proposed approach, we have also implemented an experimental system as a case study. Our experiments demonstrate that the proposed accelerator with a network interface achieves an effective throughput around 760 Mbps or equivalently nearly 6 million tuples per second, by fully utilizing the available bandwidth of the network interface.

关键词： Aggregates Registers field programmable gate arrays Hardware Clocks Out of order Pipelines

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HERA Project's Holistic Evolutionary Framework

HERA Project's Holistic Evolutionary Framework

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IEEE international symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Davide B. Bartolini Matteo Carminati Fabio Cancare Marco D. Santambrogio Donatella Sciuto Politecnico di Milano Milano Lombardia IT Dipartimento di Elettronica Informazione e Bioingegneria Politecnico di Milano

ISBN: (纸本)9781479913725

Research efforts in Evolvable Hardware allowed to prove how it is possible to adopt a radically alternative approach to the synthesis of hardware circuits by drawing inspiration from natural selection and evolution. In order to move these achievements to a new level, however, we need more sophisticated tools and support for experimenting with new structures and devices. This paper moves a first step in this direction by presenting our proposal for a holistic evolutionary framework, able to provide simple yet powerful abstractions o unify a variety of evolutionary architectures under the same comprehensive framework. This way, we allow to reuse a finely-tuned evolutionary infrastructure for any kind of architecture using our general model. Additional contribution of this work is the design and evaluation, within the holistic framework, of a novel flexible fpga-based evolutionary architecture which dispenses from the need of relying on the internal configuration access port, which proved to be a serious bottleneck in previous work.

关键词： Hardware field programmable gate arrays Routing Table lookup Evolution (biology) Software

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A Flexible Memory Controller Supporting Deep Belief Networks with Fixed-Point Arithmetic

A Flexible Memory Controller Supporting Deep Belief Networks...

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IEEE international symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Jingfei Jiang Rongdong Hu Mikel Luján School of Computer Science National University of Defense Technology Changsha China School of Computer Science University of Manchester Manchester UK

ISBN: (纸本)9781479913725

Deep Belief Networks (DBNs) are state-of-art Machine Learning techniques and one of the most important unsupervised learning algorithms. Training DBNs is computationally intensive which naturally leads to investigate fpga acceleration. Fixed-point arithmetic can have an important influence on the execution time and prediction accuracy of a DBN. Previous studies have focused only on customized DBN accelerators with a fixed data-width. Our results experiments demonstrate that supporting various data-widths in different DBN configurations and application environments does make sense for achieving acceptable performance. From this we conclude that a DBN accelerator should support various data-widths rather than the fixed one as done in previous work. The processing performance of DBN accelerators in fpga is almost always constrained not by the capacity of the processing units, but by their on-chip RAM capacity and speed. We propose an efficient memory controller for DBN accelerators, which shows that supporting various data-widths is not as difficult as it may sound. The cost is only little in hardware terms and does not affect the critical path. We have designed a tool to help users reconfiguring the memory controller with arbitrary data-width flexibly.

关键词： Random access memory field programmable gate arrays Training Educational institutions Hardware System-on-chip Approximation methods

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TinyCSE: Tiny Computer System for Education

TinyCSE: Tiny Computer System for Education

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international symposium on Computing and Networking (CANDAR)

作者： Ryosuke Nakamura Yasuaki Ito Koji Nakano Department of Information Engineering Hiroshima University Higashi Hiroshima Japan

TinyCPU is a small processor that can be implemented in various fpgas that can be used for education and development of small embedded system. TinyCPU is so small that it is designed using Verilog HDL and the size of source code is only 427 lines. However, it does not support interrupts and peripheral controllers. The main contribution of this paper is to present TinyCSE (Tiny Computer System for Education), an extension of TinyCPU supporting interrupts and peripheral controllers. TinyCSE has controllers for external devices including keyboard, mouse, serial communication, switch, and timer. It also supports hardware interrupts from these external devices. Quite surprisingly, the code sizes of the CPU with interrupt controller and the device controllers are 515 lines and is 1339 lines in Verilog HDL, respectively. Our processor is portable and easy to understand and the function expansion is not difficult. As real-life applications, we have developed a time watch. This applications runs in 73MHz on the Xilinx Spartan-3AN family fpga XC3S700AN using 832 out of 5888 slices (14.1%). Therefore, our tiny processing system benefits computer system education and small embedded system development.

关键词： field programmable gate arrays Hardware design languages Computer architecture Education Hardware Process control Switches

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Design, Implementation and Evaluation of Built-in Functions on Parallel Programming Model in SMYLE OpenCL

Design, Implementation and Evaluation of Built-in Functions ...

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IEEE international symposium on Embedded Multicore Socs (MCSoC)

作者： Noriko Etani Takuji Hieda Hiroyuki Tomiyama Research Organization of Science and Technology College of Science and Engineering Ritsumeikan University Shiga Japan

In this paper, we propose built-in functions on parallel programming model in SMYLE OpenCL to extend the original OpenCL semantics giving our system's original limitation and interpretation for embedded many-core architecture. On a platform using fpga to evaluate embedded many-core architecture SMYLEref, data parallel and task parallel programming models supported by the OpenCL execution model are implemented. Then, high-level API based on an OpenCL framework, named SMYLE OpenCL, has been developed. Math functions, integer functions, common functions, geometric functions, relational functions, and barrier function of synchronization functions in built-in functions are implemented for OpenCL version 1.2. And the routines for floating point emulation are developed in order to compute the ranges of float and double on the device core which OS is not installed in. This paper describes the design and its implementation of built-in functions on parallel programming model in SMYLE OpenCL, and shows how to solve the implementation issues. The high-speed low-power performance using parallel benchmark applications compared with a former technology is demonstrated.

关键词： Kernel Libraries Parallel programming Radiation detectors Computer architecture field programmable gate arrays Synchronization

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