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检索条件"任意字段=2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013"

共 809 条记录，以下是41-50 订阅

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PRGA: An open-source fpga research and prototyping framework 21

PRGA: An open-source fpga research and prototyping framework

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2021 acm/sigda international symposium on field-programmable gate arrays, fpga 2021

作者： Li, Ang Wentzlaff, David Princeton University PrincetonNJ United States

ISBN: (纸本)9781450382182

field programmable gate arrays (fpga) are being used in a fast-growing range of scenarios, and heterogeneous CPU-fpga systems are being tapped as a possible way to mitigate the challenges posed by the end of Moore's Law. This growth in diverse use cases has fueled the need to customize fpga architectures for particular applications or application domains. While high-level fpga models can help explore the fpga architecture space, as fpgas move to more advanced design nodes, there is an increased need for low-level fpga research and prototyping platforms that can be brought all the way to fabrication. This paper presents Princeton Reconfigurable gate Array (PRGA), a highly customizable, scalable, and complete open-source framework for building custom fpgas. The framework's core functions include generating synthesizable Verilog from user-specified fpga architectures, and providing a complete, auto-generated, open-source CAD toolchain for the custom fpgas. Developed in Python, PRGA provides a user-friendly API and supports use both as a standalone fpga as well as an embedded fpga. PRGA is a great platform for fpga architecture research, fpga configuration memory research, fpga CAD tool research, and heterogeneous systems research. It is also a completely open-source framework for designers who need a free and customizable fpga IP core. An fpga designed with PRGA is placed and routed using standard cell libraries. The design is evaluated and compared to prior works, providing comparable performance and increased configurability. © 2021 acm.

关键词： field programmable gate arrays (fpga)

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NetCracker: A peek into the routing architecture of xilinx 7-series fpgas 21

NetCracker: A peek into the routing architecture of xilinx 7...

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2021 acm/sigda international symposium on field-programmable gate arrays, fpga 2021

作者： Petersen, Morten B. Nikolić, Stefan Stojilović, Mirjana Epfl School of Computer and Communication Sciences LausanneCH-1015 Switzerland

ISBN: (纸本)9781450382182

Novel applications have triggered significant changes at the system level of fpga architecture design, such as the introduction of embedded VLIW processor arrays and hardened NoCs. However, the routing architecture of the soft logic fabric has largely remained unchanged in recent years. Since hunger for acceleration of ever more varied tasks with various power budgets-as well as complications related to technology scaling-is likely to remain significant, it is foreseeable that the routing architecture too will have to evolve. In this work, we do not try to suggest how routing architectures of tomorrow should look like. Instead, we analyze an existing architecture from a popular commercial fpga family, discussing the possible origins of various design decisions and pointing out aspects that may merit future research. Moreover, we present an open-source tool that greatly eases such analyses, relying only on data readily available from the vendor CAD tools. Our hope is that this work will help the academic research community in catching up with the current developments in industry and accelerate its contributions to fpga architectures of the future. © 2021 acm.

关键词： field programmable gate arrays (fpga)

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HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond 24

HLSFactory: A Framework Empowering High-Level Synthesis Data...

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6th international symposium on Machine Learning for CAD (MLCAD)

作者： Abi-Karam, Stefan Sarkar, Rishov Seigler, Allison Lowe, Sean Wei, Zhigang Chen, Hanqiu Rao, Nanditha John, Lizy Arora, Aman Hao, Cong Georgia Inst Technol Atlanta GA 30332 USA Georgia Tech Res Inst Atlanta GA 30332 USA Univ Texas Austin Austin TX USA Arizona State Univ Tempe AZ USA Int Inst Informat Technol Bangalore Bangalore Karnataka India

ISBN: (数字)9798350363562

ISBN: (纸本)9798400706998

Machine learning (ML) techniques have been applied to high-level synthesis (HLS) flows for quality-of-result (QoR) prediction and design space exploration (DSE). Nevertheless, the scarcity of accessible highquality HLS datasets and the complexity of building such datasets present great challenges to fpga and ML researchers. Existing datasets either cover only a subset of previously published benchmarks, provide no way to enumerate optimization design spaces, are limited to a specific vendor, or have no reproducible and extensible software for dataset construction. Many works also lack user-friendly ways to add more designs to existing datasets, limiting wider adoption and sustainability of such datasets. In response to these challenges, we introduce HLSFactory, a comprehensive framework designed to facilitate the curation and generation of high-quality HLS design datasets. HLSFactory has three main stages: 1) a design space expansion stage to elaborate single HLS designs into large design spaces using various optimization directives across multiple vendor tools, 2) a design synthesis stage to execute HLS and fpga tool flows concurrently across designs, and 3) a data aggregation stage for extracting standardized data into packaged datasets for ML usage. This tripartite architecture not only ensures broad coverage of data points via design space expansion but also supports interoperability with tools from multiple vendors. Users can contribute to each stage easily by submitting their own HLS designs or synthesis results via provided user APIs. The framework is also flexible, allowing extensions at every step via user APIs with custom frontends, synthesis tools, and scripts. To demonstrate the framework functionality, we include an initial set of built-in base designs from PolyBench, MachSuite, Rosetta, CHStone, Kastner et al.'s Parallel Programming for fpgas, and curated kernels from existing open-source HLS designs. We report the statistical analyses and design space

关键词： Solid modeling Statistical analysis Buildings Machine learning Benchmark testing Software Space exploration Sustainable development field programmable gate arrays Optimization

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S2N2: A fpga accelerator for streaming spiking neural networks 21

S2N2: A fpga accelerator for streaming spiking neural networ...

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2021 acm/sigda international symposium on field-programmable gate arrays, fpga 2021

作者： Khodamoradi, Alireza Denolf, Kristof Kastner, Ryan University of California San Diego United States Xilinx Longmont United States

ISBN: (纸本)9781450382182

Spiking Neural Networks (SNNs) are the next generation of Artificial Neural Networks (ANNs) that utilize an event-based representation to perform more efficient computation. Most SNN implementations have a systolic array-based architecture and, by assuming high sparsity in spikes, significantly reduce computing in their designs. This work shows this assumption does not hold for applications with signals of large temporal dimension. We develop a streaming SNN (S2N2) architecture that can support fixed-per-layer axonal and synaptic delays for its network. Our architecture is built upon FINN and thus efficiently utilizes fpga resources. We show how radio frequency processing matches our S2N2 computational model. By not performing tick-batching, a stream of RF samples can efficiently be processed by S2N2, improving the memory utilization by more than three orders of magnitude. © 2021 acm.

关键词： field programmable gate arrays (fpga)

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FABulous: An embedded fpga framework 21

FABulous: An embedded fpga framework

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2021 acm/sigda international symposium on field-programmable gate arrays, fpga 2021

作者： Koch, Dirk Dao, Nguyen Healy, Bea Yu, Jing Attwood, Andrew Computer Science University of Manchester United Kingdom Liverpool John Moores University United Kingdom

ISBN: (纸本)9781450382182

At the end of CMOS-scaling, the role of architecture design is increasingly gaining importance. Supporting this trend, customizable embedded fpgas are an ingredient in ASIC architectures to provide the advantages of reconfigurable hardware exactly where and how it is most beneficial. To enable this, we are introducing the FABulous embedded open-source fpga framework. FABulous is designed to fulfill the objectives of ease of use, maximum portability to different process nodes, good control for customization, and delivering good area, power, and performance characteristics of the generated fpga fabrics. The framework provides templates for logic, arithmetic, memory, and I/O blocks that can be easily stitched together, whilst enabling users to add their own fully customized blocks and primitives. The FABulous ecosystem generates the embedded fpga fabric for chip fabrication, integrates Yosys, ABC, VPR and nextpnr as fpga CAD tools, deals with the bitstream generation and after fabrication tests. Additionally, we provide an emulation path for system development. FABulous was demonstrated for an ASIC integrating a RISC-V core with an embedded fpga fabric for custom instruction set extensions using a TSMC 180nm process and an open-source 45nm process node. © 2021 acm.

关键词： field programmable gate arrays (fpga)

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Folded integer multiplication for fpgas 21

Folded integer multiplication for fpgas

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2021 acm/sigda international symposium on field-programmable gate arrays, fpga 2021

作者： Langhammer, Martin Pasca, Bogdan Intel Corporation Salisbury United Kingdom Intel Corporation France

ISBN: (纸本)9781450382182

Encryption-especially the key exchange algorithms such as RSA-is an increasing use-model for fpgas, driven by the adoption of the fpga as a SmartNIC in the datacenter. While bulk encryption such as AES maps well to generic fpga features, the very large multipliers required for RSA are a much more difficult problem. Although fpgas contain thousands of small integer multipliers in DSP Blocks, aggregating them into very large multipliers is very challenging because of the large amount of soft logic required-especially in the form of long adders, and the high embedded multiplier count. In this paper, we describe a large multiplier architecture that operates in a multi-cycle format and which has a linear area/throughput ratio. We show results for a 2048-bit multiplier that has a latency of 118 cycles, inputs data every 9th cycle and closes timing at 377MHz in an Intel Arria 10 fpga, and over 400MHz in a Stratix 10. The proposed multiplier uses 1/9 of the DSP resources typically used in a 2048-bit Karatsuba implementation, showing a perfectly linear throughput to DSP-count ratio. Our proposed solution outperforms recently reported results, in either arithmetic complexity-by making use of the Karatsuba techniques, or in scheduling efficiency-embedded DSP resources are fully utilized. © 2021 acm.

关键词： field programmable gate arrays (fpga)

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Efficient fpga modular multiplication implementation 21

Efficient fpga modular multiplication implementation

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2021 acm/sigda international symposium on field-programmable gate arrays, fpga 2021

作者： Langhammer, Martin Pasca, Bogdan Intel Corporation United Kingdom Intel Corporation France

ISBN: (纸本)9781450382182

Barrett's algorithm is the most commonly known method of performing a modular multiplication, which is the core of many modern encryption algorithms such as RSA. Barrett's algorithm requires an accurate quotient estimation which in turn requires accurate multiplications. These multiplications operating on word sizes of thousands of bits are particularly expensive to implement in fpgas, requiring many hundreds or even thousands of embedded DSP components along with large amounts of logic and routing. In this work we show that approximate quotient estimates as results of aggressive multiplier truncations can significantly reduce implementation cost. The looser modified Barrett's output [0;YM) is reduced to [0;M) using a shallow reduction technique based on table lookups and wide additions, taking advantage of new techniques which have recently been introduced for fpga. We first use these techniques to develop an improved standard Barrett's implementation for 1024b modular multiplication, followed by our approximate method which reduces logic cost in the LSB truncated multiplier by approximately 10%. The effect is more pronounced for very large word sizes, where our relaxed error bounds in the LSB truncated multiplication can reduce the number of operations by 20%. © 2021 acm.

关键词： field programmable gate arrays (fpga)

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MOCHA: Multinode cost optimization in heterogeneous clouds with accelerators 21

MOCHA: Multinode cost optimization in heterogeneous clouds w...

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2021 acm/sigda international symposium on field-programmable gate arrays, fpga 2021

作者： Zhou, Peipei Sheng, Jiayi Yu, Cody Hao Wei, Peng Wang, Jie Wu, Di Cong, Jason University of Pittsburgh United States University of California Los Angeles United States Microsoft Amazon Web Services Google Facebook

ISBN: (纸本)9781450382182

fpgas have been widely deployed in public clouds, e.g., Amazon Web Services (AWS) and Huawei Cloud. However, simply offloading accelerated kernels from CPU hosts to PCIe-based fpgas does not guarantee out-of-pocket cost savings in a pay-as-you-go public cloud. Taking Genome Analysis Toolkit (GATK) applications as case studies, although the adoption of fpgas reduces the overall execution time, it introduces 2.56× extra cost, due to insufficient application-level speedup by Amdahl's law. To optimize the out-of-pocket cost while keeping high speedup and throughput, we propose Mocha framework as a distributed runtime system to fully utilize the accelerator resource by accelerator sharing and CPU-fpga partial task offloading. Evaluation results on Haplotype Caller (HTC) and Mutect2 in GATK show that on AWS, Mocha saves on the application cost by 2.82x for HTC, 1.06x for Mutect2 and on Huawei Cloud by 1.22x, 1.52x respectively than straightforward CPU-fpga integration solution with less than 5.1% performance overhead. © 2021 acm.

关键词： field programmable gate arrays (fpga)

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HBM connect: High-performance hls interconnect for fpga hbm 21

HBM connect: High-performance hls interconnect for fpga hbm

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2021 acm/sigda international symposium on field-programmable gate arrays, fpga 2021

作者： Choi, Young-Kyu Chi, Yuze Qiao, Weikang Samardzic, Nikola Cong, Jason Department of Computer Science University of California Los Angeles United States

ISBN: (纸本)9781450382182

With the recent release of High Bandwidth Memory (HBM) based fpga boards, developers can now exploit unprecedented external memory bandwidth. This allows more memory-bounded applications to benefit from fpga acceleration. However, fully utilizing the available bandwidth may not be an easy task. If an application requires multiple processing elements to access multiple HBM channels, we observed a significant drop in the effective bandwidth. The existing high-level synthesis (HLS) programming environment had limitation in producing an efficient communication architecture. In order to solve this problem, we propose HBM Connect, a high-performance customized interconnect for fpga HBM board. Novel HLS-based optimization techniques are introduced to increase the throughput of AXI bus masters and switching elements. We also present a high-performance customized crossbar that may replace the built-in crossbar. The effectiveness of HBM Connect is demonstrated using Xilinx's Alveo U280 HBM board. Based on bucket sort and merge sort case studies, we explore several design spaces and find the design point with the best resource-performance trade-off. The result shows that HBM Connect improves the resource-performance metrics by 6.5X-211X. © 2021 acm.

关键词： field programmable gate arrays (fpga)

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Tensor slices to the rescue: Supercharging ml acceleration on fpgas 21

Tensor slices to the rescue: Supercharging ml acceleration o...

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2021 acm/sigda international symposium on field-programmable gate arrays, fpga 2021

作者： Arora, Aman Mehta, Samidh Betz, Vaughn John, Lizy K. University of Texas at Austin AustinTX United States Birla Institute of Technology and Science Pilani Goa India University of Toronto TorontoON Canada

ISBN: (纸本)9781450382182

fpgas are well-suited for accelerating deep learning (DL) applications owing to the rapidly changing algorithms, network architectures and computation requirements in this field. However, the generic building blocks available on traditional fpgas limit the acceleration that can be achieved. Many modifications to fpga architecture have been proposed and deployed including adding specialized artificial intelligence (AI) processing engines, adding support for IEEE half-precision (fp16) math in DSP slices, adding hard matrix multiplier blocks, etc. In this paper, we describe replacing a small percentage of the fpga's programmable logic area with Tensor Slices. These slices are arrays of processing elements at their heart that support multiple tensor operations, multiple dynamically-selectable precisions and can be dynamically fractured into individual adders, multipliers and MACs (multiply-and-accumulate). These tiles have a local crossbar at the inputs that helps with easing the routing pressure caused by a large slice. By spending ∼3% of fpga's area on Tensor Slices, we observe an average frequency increase of 2.45x and average area reduction by 0.41x across several ML benchmarks, including a TPU-like design, compared to an Intel Agilex-like baseline fpga. We also study the impact of spending area on Tensor slices on non-ML applications. We observe an average reduction of 1% in frequency and an average increase of 1% in routing wirelength compared to the baseline, across the non-ML benchmarks we studied. Adding these ML-specific coarse-grained hard blocks makes the proposed fpga a much efficient hardware accelerator for ML applications, while still keeping the vast majority of the real estate on the fpga programmable at fine-grain. © 2021 acm.

关键词： field programmable gate arrays (fpga)

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