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检索条件"任意字段=2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013"

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Maestro: A high performance AES encryption/decryption system

Maestro: A high performance AES encryption/decryption system

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CSI international symposium on Computer Architecture and Digital Systems

作者： Mehrdad Biglari Ehsan Qasemi Behnaz Pourmohseni Computer Engineering Department Sharif University of Technology Tehran Iran Electrical and Computer Engineering Department Campus 2 University of Tehran Tehran Iran

High throughput AES encryption/decryption is a necessity for many of modern embedded systems. This article presents a high performance yet cost efficient AES system. Maestro can be used in a wide range of embedded applications with various requirements and limitations. Maestro is about one million times faster than the pure software implementation. The Maestro architecture is composed of two major components; the soft processor aimed at system initialization and control, and the hardware AES engine for high performance AES encryption/decryption. A ten stage implicit pipelined architecture is considered for the AES engine. Two novel techniques are proposed in design of AES engine which enable it to reach a throughput of 12.8 Gbps. First, tightly coupled encryption and round key generation units in encryption unit, and second, ahead of time round key generation in decryption unit. Altera DE2-115 development and educational fpga board is used as the platform for Maestro. In the proposed architecture the DMA modules act as interfaces between data sources and data sinks by loading the input data into AES engine and taking encrypted and generated test data to target memories.

关键词： Encryption Engines Ciphers Generators Throughput field programmable gate arrays Software

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A single chip solution for pulse transmit time measurement

A single chip solution for pulse transmit time measurement

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IEEE symposium on Bioinformatics and Bioengineering (BIBE)

作者： Saša Knežević Radovan Stojanović Bogdan Ašanin Dejan Karadaglić Faculty of Electrical Engineering University of Montenegro Podgorica Montenegro School of Engineering and Built Environment Glasgow Caledonian University Glasgow United Kingdom

This paper proposes a methodology for Pulse Transmit Time measurement for purposes of cuff-less monitoring of Blood Pressure. The ECG and PPG signals are simultaneously acquired and Pulse Transmit Time is determined as a time between R peak in ECG and maximal slope in PPG. To distinguish characteristic points Discrete Wavelet Transform, Derivative Filtering, Modulus Maxima and additional functions are employed and translated in VHDL code and then embedded in a single chip from fpga technology. The system works on-line, achieving accuracy of 97.53% and 97.09% for R peak and slope detection respectively. The emphasis is given to the description of signal processing approach, system architecture and working principles of fundamental components. Also, the preliminary testing results are presented.

关键词： Detectors Electrocardiography Discrete wavelet transforms field programmable gate arrays Accuracy Approximation methods Clocks

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Design and implementation of rotation symmetric S-boxes with high nonlinearity and high DPA resilience

Design and implementation of rotation symmetric S-boxes with...

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IEEE international Workshop on Hardware-Oriented Security and Trust (HOST)

作者： Bodhisatwa Mazumdar Debdeep Mukhopadhyay Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology Kharagpur India

ISBN: (纸本)9781479905591

In this paper we propose a construction and implementation for a class of rotation-symmetric S-boxes (RSSBs) with good cryptographic properties and improved DPA resilience. The S-boxes are constructed from rotation symmetric Boolean functions (RSBFs) and these RSBFs were searched to avoid any fixed points in the RSSB maps. In literature, search of RSSBs included those consisting of fixed points which is considered to be a weakness in the S-box constructions. We present some new properties of RSSBs and find that the search space of RSSBs with fixed points is of exponential order. We also present the hardware architecture of the RSSBs with no fixed points and the corresponding implementations on Xilinx Virtex-5 fpga device on SASEBO-GII development board and perform a correlation analysis DPA of AES which include these RSSBs. The RSSBs from the proposed class when incorporated in AES, required more power traces compared to the AES containing Rijndael S-box which indicates that the DPA resilience of the proposed RSSBs is higher than that of the AES Rijndael S-box. Also we present the correlation analysis DPA results on the look-up table, distributed memory and block memory based implementations of some of the RSSBs from the proposed class and compare the results with those of the respective implementations of AES-128 Rijndael S-box.

关键词： Cryptography Amplitude modulation Resilience field programmable gate arrays Orbits

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Software Defined Radio for Passive Sensor Interrogation

Software Defined Radio for Passive Sensor Interrogation

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Joint European Frequency and Time Forum / international Frequency Control symposium (EFTF/IFC)

作者： Humphries, J. R. Malocha, D. C. Univ Cent Florida Dept Elect Engn & Comp Sci Orlando FL 32816 USA

ISBN: (纸本)9781479903429

The software defined radio (SDR) provides a unique platform to interrogate passive, wireless sensors. The SDR platform defines many radio functions in software, rather than hardware. This allows for a very versatile interrogation platform that can be quickly reconfigured for diverse scenarios. This paper investigates the Universal Software Radio Peripheral (USRP), a commercial SDR developed by Ettus Research(,(TM)) to determine its viability to interrogate passive, wireless sensors. In particular, the N200 USRP and the WBX daughterboard are considered because they allow for the greatest possible bandwidth for this platform (40MHz) and frequency tuning that is ideal for surface acoustic wave (SAW) sensor interrogation (50MHz -2.2GHz). In the default operation mode, the USRP continuously streams data to and from the host computer. The host computer generates samples for transmission and processes any received samples. Synchronization of the transmit and receive chains becomes difficult due to latency in the communication medium (USB or Ethernet) between the host and USRP. While this mode is sufficient for most narrowband applications, wideband applications are more difficult to achieve because of the high sampling rates required (even in a baseband system such as the USRP). A prototype transceiver (passive tag reader) is developed by modifying the N200 fpga to introduce new functionality to the USRP. These modifications include a custom interrogation signal generator (linear chirp) and triggering of the receiver based on the transmission state and desired listening time. These modifications are discussed and the modified transmit and receive characteristics are analyzed. Finally, a passive, wireless SAW OFC sensor is interrogated to demonstrate performance as a passive sensor transceiver.

关键词： field programmable gate arrays radio transceivers signal generators software radio surface acoustic wave sensors synchronisation tuning

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Global Atmospheric Simulation on a Reconfigurable Platform

Global Atmospheric Simulation on a Reconfigurable Platform

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Annual IEEE symposium on field-programmable Custom Computing Machines (FCCM)

作者： Lin Gan Haohuan Fu Wayne Luk Chao Yang Wei Xue Guangwen Yang Department of Computer Science and Technology Ministry of Education Key Laboratory for Earth System Modeling Center for Earth System Science Tsinghua University Beijing China Ministry of Education Key Laboratory for Earth System Modeling Center for Earth System Science Tsinghua University Beijing China Department of Computing Imperial College London London UK Institute of Software Chinese Academy of Sciences Beijing China

Summary form only given. As the only method to study long-term climate trend and to predict potential climate risk, climate modeling is becoming a key research topic among governments and research organizations. One of the most essential and challenging components in climate modeling is the atmospheric model. To cover high resolution in climate simulation scenarios, developers have to face the challenges from billions of mesh points and extremely complex algorithms. Shallow Water Equations (SWEs) are a set of conservation laws that perform most of the essential characteristics of the atmosphere. The study of SWEs can serve as the starting point for understanding the dynamic behavior of the global atmosphere. We choose cubed-sphere mesh as the computational mesh for its better load balance in pole regions over other meshes such as the latitude-longitude mesh. The cubed-sphere mesh is obtained by mapping a cube to the surface of the sphere. The computational domain is then the six patches, each of which is covered with N × N mesh points to be calculated. When written in local coordinates, SWEs have an identical expression on the six patches, that is ∂Q/∂t + 1/Λ ∂(ΛF 1 )/∂x 1 + 1/Λ ∂(ΛF 1 )/∂z 2 + S=0, (1) where (x 1 , x 2 ) ∈ [-π/4, π/4] are the local coordinates, Q = (h, hu 1 , hu 2 ) T is the prognostic variable, F i = u i Q (i = 1, 2) are the convective fluxes, S is the source term. Spatially discretized with a cell-centered finite volume method and integrated with a second-order accurate TVD Runge-Kutta method, SWE solvers are transferred to the computation of a 13-point upwind stencil that exhibits a diamond shape. To get the prognostic components (h, hu 1 and hu 2 ) of the central point, its neighboring 12 points need to be accessed. The stencil kernel includes at least 434 ADD/SUB operations, 570 multiplications, 99 divisions. The high arithmetic density of the SWEs algorithm makes it difficult to implement one kernel into the resource-limited fpga card. I

关键词： Atmospheric modeling field programmable gate arrays Mathematical model Meteorology Kernel Educational institutions Equations

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A Compiler for Scalable Placement and Routing of Brain-like Architectures 13

A Compiler for Scalable Placement and Routing of Brain-like ...

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international symposium on Physical Design

作者： Narayan Srinivasa HRL Laboratories LLC Malibu CA USA

ISBN: (纸本)9781450318679

The challenging aspect of building neuromorphic circuits in mature CMOS technology to match brain-like architectures is two-fold: scalability and connectivity. Scalability means that the circuits have to be expandable to match biological brains in terms of synaptic and neuronal densities. The challenge here is to implement 10~6 neurons and 10~(10) synapses with an average fanout of 10~4, in a square cm of CMOS. Connectivity means that the circuit has to offer the capability to have both short and long range (by physical distance) connections between neurons. A large part of this challenge is how to implement a connectivity of 10~4 synapses per neuron. Unfortunately, even the exponential transistor density growth being experienced today is not sufficient to realize such massive connectivity and synaptic densities in a traditional CMOS process. Recent approaches to address these challenges have been to integrate CMOS with nanotechnology in order to achieve the required synaptic densities. These solutions use crossbar architectures predominantly but the connectivity challenge still remains a daunting task for such solutions. To meet these challenges, a novel synaptic time-multiplexing (STM) concept was developed along with a neural fabric design. This combination has the advantage of offering greater flexibility and long range connectivity. It also provides a method to overcome the limitations of conventional CMOS technology to match the synaptic density and connectivity requirements found in mammalian brains while maintaining nonlinear synapses and learning. In order to program neuromorphic hardware for any desired brain architecture, the topology would first have to be converted into a connectivity matrix or a graph representation. This matrix along with the statistics on the number of neurons and synapses is provided as input to a neuromorphic compiler. The neuromorphic compiler compiles the neural network structure description into: 1) an assignment of the network'

关键词： Routing Placement Brain-like Architectures Compiler Network routing compilers Neuromorphics placement Synapses Neurons ARCHITECTURE Cerebrum field programmable gate arrays CMOS technology Building construction Synaptic density

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fpga-based implementation of the back-EMF symmetric-threshold-tracking sensorless commutation method for Brushless DC-machines

FPGA-based implementation of the back-EMF symmetric-threshol...

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Sensorless Control for Electrical Drives (SLED)

作者： Araz Darba Frederik De Belie Aboubakr Salem Jan Melkebeek Department of Electrical Energy Systems and Automation of Ghent University Belgium

The operation of brushless DC permanent-magnet machines requires information of the rotor position to steer the semiconductor switches of the power-supply module which is commonly referred to as Brushless Commutation. Different sensorless techniques have been proposed to estimate the rotor position using current and voltage measurements of the machine. Detection of the back-electromotive force (EMF) zero-crossing moments is one of the methods most used to achieve sensorless control by predicting the commutation moments. Most of the techniques based on this phenomenon have the inherit disadvantage of an indirect detection of commutation moments. This is the result of the commutation moment occurring 30 electrical degrees after the zero-crossing of the induced back-emf in the unexcited phase. Often, the time difference between the zero crossing of the back-emf and the optimal current commutation is assumed constant. This assumption can be valid for steady-state operation, however a varying time difference should be taken into account during transient operation of the BLDC machine. This uncertainty degrades the performance of the drive during transients. To overcome this problem which improves the performance while keeping the simplicity of the back-emf zero-crossing detection method an enhancement is proposed. The proposed sensorless method operates parameterless in a way it uses none of the brushless dc-machine parameters. In this paper different aspects of experimental implementation of the new method as well as various aspects of the fpga programming are discussed. Proposed control method is implemented within a Xilinx Spartan 3E XC3S500E board.

关键词： Commutation Voltage measurement field programmable gate arrays Inverters Delays Rotors Current measurement

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A Hardware Approach for Solving the Robot Localization Problem Using a Sequential EKF

A Hardware Approach for Solving the Robot Localization Probl...

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IEEE international symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Sérgio Cruz Daniel M. Muñoz Milton E. Conde Carlos H. Llanos Geovany A. Borges Department of Mechanical Engineering Faculty of Gama Electronics Engineering Graduate Program Department of Electrical Engineering University of Brasilia Brasília D.F Brazil

This work describes a hardware architecture for implementing a sequential approach of the Extended Kalman Filter (EKF) that is suitable for mobile robotics tasks, such as self-localization, mapping and navigation problems. As such algorithm is computationally intensive, commonly it is implemented in PC-based platforms to be employed on larger robots. In order to allow the development of small robotic platforms, as those required in many current state of the art research (for instance micro robotics area), small size, low-power and high precision computation capabilities are required. This work proposes a hardware architecture for self-localization task, allowing the fusion of data coming from different sensors such as ultrasonic and laser rangefinder. The architecture is based on a single precision floating-point arithmetic, allowing the operations to be computed with large precision and dynamic range. The system has been adapted for achieving a reconfigurable platform, suitable for research tasks, and applied to a Pioneer 3AT mobile robot platform from Mobile Robots Inc. In order to compare the performance of the system, the same localization technique has been implemented in a high-end PC, as well as using an embedded microprocessor Nios II from Alter a Inc. In this paper several metrics have been used to evaluate system performance and suitability, measuring fpga resources consumption and performance. Finally, the suitability of reconfigurable devices for such kind of applications has been verified and also discussed.

关键词： field programmable gate arrays Hardware Kalman filters Robot sensing systems Sensor fusion

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A High-Level Synthesis and Verification Tool for Application Specific k~(th) Root Processing Engine

A High-Level Synthesis and Verification Tool for Application...

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IEEE international Midwest symposium on Circuits and Systems

作者： Semih Aslan Hassan Salamy Jafar Saniie Ingram School of Engineering Electrical Engineering Texas State University Department of Electrical and Computer Engineering Illiniois Institute of Technology

ISBN: (纸本)9781479900657

Implementation of division, square root, and cube root and their inverses at the hardware level creates a number of bottlenecks in terms of accuracy, speed and design verification in particular. There are many DSP and communication systems in which these arithmetic operations are used. Therefore, a Newton-Raphson algorithm based, efficient, accurate and reconfigurable k~(th) root design and verification system is introduced. The design and verification system generates Verilog HDL design code and required control signals for application-specific operations. The design can be used for multi-purpose arithmetic operations based on an assigned k value, such as division for k=1, square root for k=2, cube root for k=3 and so on. The generated hardware can be used as a standalone design or can be implemented into a larger system by using a hand shake signal, which could make this design and verification tool suitable for new or ongoing projects. This tool generates Verilog RTL code and its testbench that can be implemented in fpgas and VLSI systems. The proposed design tool can increase productivity by reducing design and verification time. Several case studies have been implemented on Xilinx Virtex-5 fpgas. The designed system uses MATLAB-based verification and reporting for fast and accurate design evaluation.

关键词： fpga VLSI Division Square-root Newton-Raphson Method K~(th) root Inverse k~(th) root Newton-Raphson method Square root Very large scale integration field programmable gate arrays verification system Division cubic root Hardware design languages hardware level division Verification design verification design assessment high level synthesis Custom design

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A Flexible-Length-Arithmetic Processor Using Embedded DSP Slices and Block RAMs in fpgas

A Flexible-Length-Arithmetic Processor Using Embedded DSP Sl...

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international symposium on Computing and Networking (CANDAR)

作者： Md. Nazrul Islam Mondal Kohan Sai Koji Nakano Yasuaki Ito Department of Information Engineering Hiroshima University Higashi-Hiroshima Japan

Some applications such as RSA encryption/decryption needs integer arithmetic operations with many bits. However, such operations cannot be performed directly by conventional CPUs, because their instruction supports integers with fixed bits, say, 64 bits. Since the CPUs need to repeat arithmetic operations to numbers with fixed bits, they have considerably overhead to execute applications involving integer arithmetic with many bits. On the other hand, we can implement hardware algorithms for such applications in the fpgas for further acceleration. However, the implementation of hardware algorithm is usually very complicated and debugging of hardware is too hard. The main contribution of this paper is to present an intermediate approach of software and hardware using fpgas. More specifically, we present a processor based on FDFM (Few DSP slices and Few Memory blocks) approach that supports arithmetic operations with flexibly many bits, and implement it in the fpga. Arithmetic instructions of our processor architecture include addition, subtraction, and multiplication for numbers with variable size longer than 64 bits. To show the potentiality of our processor, we have implemented 2048-bit RSA encryption/decryption by software written by machine instructions. The resulting processor uses only one DSP48E1 slices and four Block RAMs (BRAMs), and RSA encryption software on it runs in 635.65ms. It has been shown that the direct hardware implementation of RSA encryption runs in 277.26ms. Although our intermediate approach is slower, it has several advantages. Since the algorithm is written by software, the development and the debugging are easy. Also, it is more flexible and scalable.

关键词： field programmable gate arrays Hardware Digital signal processing Random access memory Software Debugging Software algorithms

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