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检索条件"任意字段=2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013"

共 809 条记录，以下是501-510 订阅

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Canonical ordering of instances to immunize the fpga place and route flow from ECO-induced variance

Canonical ordering of instances to immunize the FPGA place a...

引用

IEEE international symposium on Quality Electronic Design

作者： Avijit Dutta Neil Tuttle Krishnan Anandh Cypress Semiconductor OR USA

Engineering change order (ECO)s for fpga-based designs often require design changes late in the design process in order to correct functional, timing, and/or technological problems. Typically, after an ECO process a small portion of the circuit netlist is changed. To take advantage of the enormous resources and time already spent on place and route flow, it is desirable to maintain similar post-routing delay characteristics to the pre-ECO stage to avoid further expensive design iterations. Most fpga tools use the variance to their advantage to explore the solution space in the design optimization phase. fpga companies can afford to run multiple passes and just retain the best solution. The embedded systems companies cannot afford multiple pass compile times especially in ECO situations. Note that the variance reduction technique proposed in this paper is applicable only in the ECO situations and not during design optimization phase where variance plays an advantageous role. Predictability is not just unique to ECO, but success of an ECO is highly dependent on predictability and that's where the proposed approach plays a crucial role. The ECO process may change a small subset of the circuit netlist, which may result in a minor variation in the instance list order seen by the packer. Most packing heuristics, including fast greedy heuristics as well as relatively slower non-greedy heuristics, process the input netlist in a certain order and have varying degrees of dependence on the initial instance order. Even a slight variation may result in a substantially different packing and the subsequent placement and routing results may also change. In the worst case, the post-routing delay may fail timing constraints and require inexpensive design iteration. In this paper, we propose a fast canonical ordering technique that either guarantees a unique instance order if the ECO process caused a change in the initial instance order or minimizes the perturbation to the instance or

关键词： field programmable gate arrays Delays Routing Noise Algorithm design and analysis Table lookup

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A new design paradigm for floating point DSP applications based on ESL/HLS and fpgas?

A new design paradigm for floating point DSP applications ba...

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IEEE international symposium on Signal Processing and Information Technology (ISSPIT)

作者： Dionysios Diamantopoulos Christoforos Economakos Dimitrios Soudris George Economakos National Technical University of Athens Heroon Polytechniou 9 Athens Greece Department of Automation Engineering Technological Educational Institution of Sterea Ellada Psahna Evia Greece

Digital signal processing has emerged in every aspect of modern life, with different implementations found in appliances ranging from simple answering machines to high speed multimedia cloud routers. The design of such appliances requires a number of decision steps, based on diverse criteria like time-to-market, development cost, production cost, production volume, performance, power consumption and algorithm complexity, to name just a few. A crucial decision step is the use of a floating or fixed-point number representation. This paper presents a new paradigm for the design of floating point applications, based on modern hardware design techniques like electronic system level design and high-level synthesis, and the computing capabilities and power efficiency of modern fpga devices. Specifically, it presents the design of a reusable, floating point, hardware operator library, starting from an open source software implementation. The advantages of this new paradigm is productivity improvement and ease of integration, through the use (or reuse) of C level input specifications, and performance improvements, by applying a set of specific C level hardware coding guidelines. As found through extensive experimentation, performance and area optimizations offered by these guidelines can be even more than 90%. Such results make the presented methodology an appealing and very promising design alternative.

关键词： Optimization Hardware Digital signal processing field programmable gate arrays Encoding Guidelines Schedules

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Software defined radio for passive sensor interrogation

Software defined radio for passive sensor interrogation

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IEEE international Frequency Control symposium

作者： J. R. Humphries D. C. Malocha Department of Electrical Engineering and Computer Science University of Central Florida Orlando FL

The software defined radio (SDR) provides a unique platform to interrogate passive, wireless sensors. The SDR platform defines many radio functions in software, rather than hardware. This allows for a very versatile interrogation platform that can be quickly reconfigured for diverse scenarios. This paper investigates the Universal Software Radio Peripheral (USRP), a commercial SDR developed by Ettus Research TM , to determine its viability to interrogate passive, wireless sensors. In particular, the N200 USRP and the WBX daughterboard are considered because they allow for the greatest possible bandwidth for this platform (40MHz) and frequency tuning that is ideal for surface acoustic wave (SAW) sensor interrogation (50MHz-2.2GHz). In the default operation mode, the USRP continuously streams data to and from the host computer. The host computer generates samples for transmission and processes any received samples. Synchronization of the transmit and receive chains becomes difficult due to latency in the communication medium (USB or Ethernet) between the host and USRP. While this mode is sufficient for most narrowband applications, wideband applications are more difficult to achieve because of the high sampling rates required (even in a baseband system such as the USRP). A prototype transceiver (passive tag reader) is developed by modifying the N200 fpga to introduce new functionality to the USRP. These modifications include a custom interrogation signal generator (linear chirp) and triggering of the receiver based on the transmission state and desired listening time. These modifications are discussed and the modified transmit and receive characteristics are analyzed. Finally, a passive, wireless SAW OFC sensor is interrogated to demonstrate performance as a passive sensor transceiver.

关键词： Chirp field programmable gate arrays Surface acoustic waves Delays Wireless sensor networks Wireless communication Bandwidth

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fpga'10 - Proceedings of the 18th acm sigda international symposium on field-programmable gate arrays

FPGA'10 - Proceedings of the 18th ACM SIGDA International Sy...

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18th acm sigda international symposium on field-programmable gate arrays, fpga'10

ISBN: (纸本)9781605589114

The proceedings contain 34 papers. The topics discussed include: fpga prototyping of an AMBA-based Windows-compatible SoC;predicting the performance of application-specific NoCs implemented on fpgas;energy efficient sensor node implementations;high throughput and large capacity pipelined dynamic search tree on fpga;FPMR: MapReduce framework on fpga: a case study of RankBoost acceleration;Axel: a heterogeneous cluster with fpgas and GPUs;building a faster Boolean matcher using bloom filter;scalable network virtualization using fpgas;maximizing area-constrained partial fault tolerance in reconfigurable logic;fpga based chip emulation system for test development and verification of analog and mixed signal circuits;a semi-automatic Toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning;and a dependency graph based methodology for parallelizing HLL applications on fpga.

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Built-in Self-Repair in a 3D Die Stack Using programmable Logic

Built-in Self-Repair in a 3D Die Stack Using Programmable Lo...

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IEEE international symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

作者： Kundan Nepal Xi Shen Jennifer Dworak Theodore Manikas R. Iris Bahar School of Engineering University of St Thomas Department of Computer Science and Engineering Southern Methodist University School of Engineering Brown University

ISBN: (纸本)9781479915842

3D stacked integrated circuits hold great promise for increasing system performance, but difficulties in testing dies and assembling a 3D stack are leading to yield issues and slowing the large scale manufacture of these devices. We propose helping to mitigate these issues by repairing the stack with programmable logic in fpgas that have already been included in the stack for other purposes. Specifically, we propose bypassing the defective portion of a die by replacing the defective functionality with functionality on the fpga. In this paper, we focus on the replacement of selected defective functional units in an out-of-order microprocessor. Our simulation results show that not only can we salvage a device that would otherwise have to be discarded, but creating multiple copies of the defective partition in the fpga can allow us to regain performance even when the latency of the units in the fpga is longer than that of the original defective copy.

关键词： field programmable gate arrays Maintenance engineering Application specific integrated circuits Three-dimensional displays Benchmark testing Pipelines Clocks

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Novel Fine Tunable Multichannel All-Digital Transmitter

Novel Fine Tunable Multichannel All-Digital Transmitter

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IEEE/MTT-S international Microwave symposium

作者： Nelson V. Silva Arnaldo S. R. Oliveira Nuno Borges Carvalho Departamento de Electronica Telecomunicacoes e Informatica Instituto de Telecomunicacoes Universidade de Aveiro

ISBN: (纸本)9781467361750

All-digital transmitters are gaining an increased research importance due to the unparalleled proliferation of dissimilar wireless standards and more recently due to the white space technology needs. In this paper, a new fine tunable multi-channel transmitter is presented. This new architecture supports concurrent multi-rate, multi-band, multi-standard transmission and significantly minimizes the output frequencies restrictions of current approaches by allowing fine frequency tuning for channel selection. The obtained results show the feasibility and potential of fpga-embedded RF transmitters where the use of polyphase datapaths substantially improves the SNR of the desired signals.

关键词： Cognitive radio Delta-sigma modulation field-programmable gate arrays Radio transmitters Software radio

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acm/sigda international symposium on field programmable gate arrays - fpga: Foreword

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - fpga 2010年 iii页

作者： Cheung, Peter Wawrzynek, John Imperial College London United Kingdom University of California Berkeley CA United States

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A field programmable array core for image processing (abstract only) 12

A field programmable array core for image processing (abstra...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Declan Walsh Piotr Dudek The University of Manchester Manchester United Kingdom

ISBN: (纸本)9781450311557

Massively parallel processor arrays have been shown to be an effective and suitable choice for image processing tasks [1]. More recently, some of the state of the art processor arrays have been used for real-time machine vision tasks such as intelligent transport system applications [2] or video processing on mobile applications [3] providing a much more powerful solution than a conventional processor. A number of Single Instruction Multiple Data (SIMD) processor arrays have been implemented on fpgas [4]-[6], which are particularly suited to implementing such processor architectures because of their similarities of both being arrays of fine grained logic elements. In this work, we propose an fpga implementation of a processor array where the processing elements (PEs) are as small as possible, while providing local memory sufficient for processing greyscale images. The PE is then replicated to form an array. A 32 × 32 PE array is implemented on a Xilinx Virtex 5 XC5VLX50 fpga using the four-neighbour connectivity with the possibility to scale up using a larger fpga. The processor array operates at a frequency of 96 MHz and executes a peak of 98.3 giga operations per second (GOPS) (bit-serial operations). A binary edge detection algorithm is performed in 52.08 ns. Uploading and downloading a binary image in a 32 × 32 array takes an extra 687.5 ns. Sobel edge detection of an 8-bit greyscale image is performed in 5.33 µs. Uploading and downloading an 8-bit greyscale image in a 32 × 32 array takes 5.36 µs. With larger fpgas being available in the future, the array sizes comparable to state of the art custom designed ICs can be implemented on these fpgas.

关键词： architecture fpga simd image processor array

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Power-aware fpga technology mapping for programmable-VT architectures (abstract only) 12

Power-aware FPGA technology mapping for programmable-VT arch...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Wei Ting Loke Yajun Ha Xilinx Asia Pacific Pte. Ltd. & National University of Singapore Singapore Singapore National University of Singapore Singapore Singapore

ISBN: (纸本)9781450311557

In this paper, we present a framework for leakage power reduction in fpgas with programmable-VT architectures, with focus on dual-VT technology mapping. The use of Reverse Back Bias (RBB) circuit techniques is recognized as one of the possible strategies in mitigating leakage power, a critical problem in circuits deploying deep submicron process technologies. fpgas with the ability to tune LUT VT via RBB offer the potential of reducing leakage power with no sacrifice to circuit speed. Today, Altera's Stratix line of fpgas oer some levels of VT programmability, but with optimizations limited to the post-P&R stage. We present a novel technology mapper (RBBMap), logic block packer (RBBPack) and placement-and-routing tool (RBBVPR) that together demonstrate the advantages in moving RBB optimizations upwards to the technology mapping level. Compared to an existing power-optimized technology mapping tool Emap, our framework oers an average of 44.41% savings in average logic block leakage power and 30.88% savings in average total energy consumption. We also illustrate why our work is potentially superior to another comparable work DVMap-2 that utilizes a dual-VDD approach.

关键词： fpga multiple voltage programmable-vt dual-vt reverse back bias technology mapping

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Thermal and Power Characterization of field-programmable gate arrays 11

Thermal and Power Characterization of Field-Programmable Gat...

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19th Annual acm international symposium on field-programmable gate arrays

作者： Nowroz, Abdullah Nazma Reda, Sherief Brown Univ Sch Engn Providence RI 02912 USA

ISBN: (纸本)9781450305549

In this paper we propose new techniques for thermal and power characterization of field programmable gate arrays (fpgas) using infrared imaging techniques. For thermal characterization, we capture the thermal emissions from the backside of an fpga chip during operation. We analyze the captured emissions and quantify the extent of thermal gradients and hot spots in fpgas. Given that fpgas are fabricated with no knowledge of the potential field designs, we propose soft sensing techniques that can combine the measurements of hard sensors to accurately estimate the temperatures where no sensors are embedded. For power characterization, we propose algorithmic techniques to invert the thermal emissions from fpgas into spatial power estimates. We demonstrate how this technique can be used to produce spatial power maps of soft processors during operation.

关键词： Thermal characterization sensors power mapping

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