This paper presents the implementation of a high resolution time-to-digital converter (TDC) on a dynamically reconfigurable fpga. The TDC architecture is based on the Vernier method using two ring oscillators with sli...
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ISBN:
(纸本)9781605589114
This paper presents the implementation of a high resolution time-to-digital converter (TDC) on a dynamically reconfigurable fpga. The TDC architecture is based on the Vernier method using two ring oscillators with slightly different frequencies. The proposed oscillators can be calibrated with picoseconds resolution by taking advantage of partial reconfiguration, and moreover recalibrated over time. The results obtained on a Xilinx Virtex-II Pro fpga show that the proposed TDC implementation can achieve unprecedented resolutions (on fpga) as low as 5ps and precisions up to 25ps.
Decoding operation is one of the major performance bottlenecks in network coding applications. To address the problem caused by decoding delay, this paper proposes high-performance decoding logic on the field-programm...
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ISBN:
(纸本)9781605589114
Decoding operation is one of the major performance bottlenecks in network coding applications. To address the problem caused by decoding delay, this paper proposes high-performance decoding logic on the field-programmablegate-array (fpga). A Galois field arithmetic logic unit (GF ALU) is implemented with a full parallelization. We claim that the complexity of hardware is reduced by use of the log and anti-log tables. In addition, the fast arithmetic operation is achieved by the parallelized GF ALU architecture, which allows one-row-calculations of a matrix to be performed concurrently. The decoders for four different sizes of the coefficient matrix have been implemented while the degree of parallelism is preserved for each size. The performance is evaluated by comparing with the performance of the decoding operation both on the ARM processor emulator and a real ARM processor. Using a modern Xilinx Virtex-5 device, the decoding time of 3.5 ms for the size 16 x 16 and 190.5 ms for 128 x 128 has been achieved at the operating frequency of 50MHz, which is equal to 12.7 and 21.7 in terms of speedup.
This paper describes a bus mastering implementation of the PCI Express protocol using a Xilinx fpga. While the theoretical peak performance of PCI Express is quite high, attaining that performance is a complex endeavo...
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ISBN:
(纸本)9781605584102
This paper describes a bus mastering implementation of the PCI Express protocol using a Xilinx fpga. While the theoretical peak performance of PCI Express is quite high, attaining that performance is a complex endeavor on top of an already complex protocol. The implementation is described and its performance is analyzed. Source code is offered for free download via the web. Copyright 2009 acm.
This article presents the performance evaluation of two new diagonal routing tracks in fpgas. We discuss the automatic detailed architecture generation issues and propose changes in the conventional placement and rout...
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ISBN:
(纸本)9781605584102
This article presents the performance evaluation of two new diagonal routing tracks in fpgas. We discuss the automatic detailed architecture generation issues and propose changes in the conventional placement and routing to suit these architectures better. We conduct a series of experiments on these architecture with MCNC Benchmarks, where key parameters are varied over practical ranges and we conclude that the results are well in accordance, as predicted by the theory. Copyright 2009 acm.
In this paper, we present and analyze a sophisticated communication architecture that allows to integrate many different modules into a system by fpga reconfiguration at runtime. Furthermore, we examine how this archi...
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ISBN:
(纸本)9781605584102
In this paper, we present and analyze a sophisticated communication architecture that allows to integrate many different modules into a system by fpga reconfiguration at runtime. Furthermore, we examine how this architecture can be implemented on low-cost Spartan-3 devices. It will be demonstrated that modules can be exchanged in a system without disturbing the communication architecture. The paper points out, that the capabilities of Spartan-3 fpgas are sufficient to build complex reconfigurable systems. Copyright 2009 acm.
This paper describes an analytical model that relates the architectural parameters of an fpga to the average prerouting wirelength of an fpga implementation. Both homogeneous and heterogeneous fpgas are considered. Fo...
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ISBN:
(纸本)9781605584102
This paper describes an analytical model that relates the architectural parameters of an fpga to the average prerouting wirelength of an fpga implementation. Both homogeneous and heterogeneous fpgas are considered. For homogeneous fpgas, the model relates the lookup-table size, the cluster size, and the number of inputs per cluster to the expected wirelength. For heterogeneous fpgas, the number and positioning of the embedded blocks, as well as the number of pins on each embedded block is considered. Two applications of the model to fpga architectural design are also presented. Copyright 2009 acm.
Technology mapping is an important step in the fpga CAD flow in which a network of simple gates is converted into a network of logic blocks. We consider enhancements to a traditional LUTbased mapping algorithm for an ...
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ISBN:
(纸本)9781605584102
Technology mapping is an important step in the fpga CAD flow in which a network of simple gates is converted into a network of logic blocks. We consider enhancements to a traditional LUTbased mapping algorithm for an fpga comprised of logic blocks which implement only a subset of functions of up to k variables- specifically, the logic block is a partial LUT, but it possesses more inputs than typical LUTs. Numerical results are presented to demonstrate the efficacy of our proposed techniques using real circuits mapped to a commercial fpga architecture. Copyright 2009 acm.
PERG is a pattern matching engine designed for locating predefined byte string patterns (rules) from ClamAV virus signature database in a data stream. This paper presents PERG-Rx, an extension of PERG that adds limite...
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ISBN:
(纸本)9781605584102
PERG is a pattern matching engine designed for locating predefined byte string patterns (rules) from ClamAV virus signature database in a data stream. This paper presents PERG-Rx, an extension of PERG that adds limited regular expression support for wildcard patterns used by rules that represent polymorphic viruses. To reduce the amount of state needed to track so many regular expressions, PERG-Rx employs a lossy scheme which increases the rate of false positives detected as the required state grows. The scalability and dynamic updatability of the PERG-Rx architecture to database updates are also evaluated. Copyright 2009 acm.
We present in this paper the first reported fpga implementation of the Position Specific Iterated BLAST (PSI-BLAST) algorithm. The latter is a heuristic biological sequence alignment algorithm that is widely used in t...
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ISBN:
(纸本)9781605584102
We present in this paper the first reported fpga implementation of the Position Specific Iterated BLAST (PSI-BLAST) algorithm. The latter is a heuristic biological sequence alignment algorithm that is widely used in the bioinformatics and computational biology world in order to detect weak homologs. The architecture of our fpga implementation is parameterized in terms of sequence lengths, scoring matrix, gap penalties and cut-off and threshold values. It is composed of various blmocks each of which performs one step of the algorithm in parallel. This results in high performance implementations, which easily outperform equivalent software implementations by one order of magnitude or more. Furthermore, the core was captured in an fpga-platformindependent language, namely the Handel-C language, to which no specific resource inference or placement constraints were applied. This makes our core portable across different fpga families and architectures. Copyright 2009 acm.
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