The paper presents several improvements to state-of-the-art in fpga technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD '04]. Improved cut enumeration computes all K-...
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ISBN:
(纸本)1595932925
The paper presents several improvements to state-of-the-art in fpga technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD '04]. Improved cut enumeration computes all K-feasible cuts without pruning for up to 7 inputs for the largest MCNC benchmarks, A new technique for on-the-fly cut dropping reduces by orders of magnitude memory needed to represent cuts for large designs. Improved area recovery leads to mappings with area on average 7% smaller than DAOmap, while preserving delay optimality when starting from the same optimized netlists. Applying mapping with structural choices derived by a synthesis flow on average reduces delay by 7% and area by 14%, compared to DAOmap. Copyright 2006 acm.
programmable logic devices such as fpgas are useful for a wide range of applications. However, fpgas are not commonly used in battery-powered applications because they consume more power than ASICs and lack power mana...
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ISBN:
(纸本)1595932925
programmable logic devices such as fpgas are useful for a wide range of applications. However, fpgas are not commonly used in battery-powered applications because they consume more power than ASICs and lack power management features. In this paper, we describe the design and implementation of Pika, a low-power fpga core targeting battery-powered applications such as those in consumer and automotive markets. Our design uses the Xilinx Spartan-3 low-cost fpga as a baseline and achieves substantial power savings through a series of power optimizations. The resulting architecture is compatible with existing commercial design tools. The implementation is done in a 90nm triple-oxide CMOS process. Compared to the baseline design, Pika consumes 46% less active power and 99% less standby power. Furthermore, it retains circuit and configuration state during standby mode, and wakes up from standby mode in approximately 100ns. Copyright 2006 acm.
The high unit cost of fpga devices often deters their use beyond the prototyping stage. Efforts have been made to reduce the part-cost of fpga devices, resulting in the development of Design-Specific fpgas. These part...
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ISBN:
(纸本)1595932925
The high unit cost of fpga devices often deters their use beyond the prototyping stage. Efforts have been made to reduce the part-cost of fpga devices, resulting in the development of Design-Specific fpgas. These parts offer cost reductions by limiting manufacturing tests and improving the number of working devices in a wafer. This paper addresses the issue of yield enhancement in Design-Specific fpgas. In this paper, an analytical model predicting the probability of mapping a specific design onto potentially defective fpgas is developed. When combined with existing yield modelling techniques, a quantitative measure of the potential yield improvements of the Design-Specific fpga approach is reported for current and future technology nodes. It is found that this approach, while beneficial with current manufacturing technology, may not be suitable for 22nm technology or beyond. Copyright 2006 acm.
The performance benefits of a monolithically stacked 3D-fpga, whereby the programming overhead of an fpga is stacked on top of a standard CMOS layer containing the logic blocks and interconnects, are investigated. A V...
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ISBN:
(纸本)1595932925
The performance benefits of a monolithically stacked 3D-fpga, whereby the programming overhead of an fpga is stacked on top of a standard CMOS layer containing the logic blocks and interconnects, are investigated. A Virtex-II style 2D-fpga fabric is used as a baseline for quantifying the relative improvements in logic density, delay, and power consumption achieved by such a 3D-fpga. It is assumed that only the pass-transistor switches and configuration memory cells can be moved to the top layers and that the 3D-fpga employs the same logic block and programmable interconnect architecture as the baseline 2D-fpga. Assuming a configuration memory cell that is ≤ 0.7 the area of an SRAM cell and pass-transistor switches having the same characteristics as nMOS devices in the CMOS layer are used, it is shown that a monolithically stacked 3D-fpga can achieve 3.2 times higher logic density, 1.7 times lower critical path delay, and 1.7 times lower total dynamic power consumption than the baseline 2D-fpga fabricated in the same 65nm technology node. Copyright 2006 acm.
This paper presents experimental measurements of the differences between a 90nm CMOS fpga and 90nm CMOS Standard Cell ASICs in terms of logic density, circuit speed and power consumption. We are motivated to make thes...
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ISBN:
(纸本)1595932925
This paper presents experimental measurements of the differences between a 90nm CMOS fpga and 90nm CMOS Standard Cell ASICs in terms of logic density, circuit speed and power consumption. We are motivated to make these measurements to enable system designers to make better informed choices between these two media and to give insight to fpga makers on the deficiencies to attack and thereby improve fpgas. In the paper, we describe the methodology by which the measurements were obtained and we show that, for circuits containing only combinational logic and flipflops, the ratio of silicon area required to implement them in fpgas and ASICs is on average 40. Modern fpgas also contain "hard" blocks such as multiplier/accumulators and block memories and we find that these blocks reduce this average area gap significantly to as little as 21. The ratio of critical path delay, from fpga to ASIC, is roughly 3 to 4, with less influence from block memory and hard multipliers. The dynamic power consumption ratio is approximately 12 times and, with hard blocks, this gap generally becomes smaller. Copyright 2006 acm.
Embedded memory blocks are important resources in contemporary fpga devices. When targeting fpgas, application designers often specify high-level memory functions which exhibit a range of sizes and control structures....
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ISBN:
(纸本)1595932925
Embedded memory blocks are important resources in contemporary fpga devices. When targeting fpgas, application designers often specify high-level memory functions which exhibit a range of sizes and control structures. These logical memories must be mapped to fpga embedded memory resources such that physical design objectives are met. In this work a set of power-aware logical-to-physical RAM mapping algorithms are described which convert user-defined memory specifications to on-chip fpga memory block resources. These algorithms minimize RAM dynamic power by evaluating a range of possible embedded memory block mappings and selecting the most power-efficient choice. Our automated approach has been integrated into a commercial fpga compiler and tested with 40 large fpga benchmarks. Through experimentation, we show that, on average, embedded memory dynamic power can be reduced by 21% and overall core dynamic power can be reduced by 7% with a minimal loss (1%) in design performance. Copyright 2006 acm.
While previous research has shown that fpgas can efficiently inclement many types of computations, their flexibility inherently limits their clock rate. Several research groups have attempted to address this by develo...
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ISBN:
(纸本)1595932925
While previous research has shown that fpgas can efficiently inclement many types of computations, their flexibility inherently limits their clock rate. Several research groups have attempted to address this by developing new architectures that include registered switchpoints within their interconnect. Unfortunately, this pipelined communication presents a new and difficult problem for detailed routing tools. Known as the N-Delay Routing Problem, it has been proven to be NP-Complete. Although there have been two heuristics developed to address this issue, both have certain limitations and neither approach considers timing during the routing process. While timing-driven conventional routing is largely considered to be a solved problem, there are several issues inherent to the N-Delay Routing problem make addressing timing particularly difficult, m this paper we discuss the nature of these problems and present a new timing-driven pipeline-aware router that produces as much as 60% better critical path delay than previous efforts. Copyright 2006 acm.
A framework that relates the size of fpga reconfiguration data to the number of minterms of a specially constructed function is presented. Three techniques, variable mapping optimization, circuit don't-care modifi...
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ISBN:
(纸本)0769525237
A framework that relates the size of fpga reconfiguration data to the number of minterms of a specially constructed function is presented. Three techniques, variable mapping optimization, circuit don't-care modification, and look-up table input permutation, are developed to minimize minterms of the special function. The method to integrate the proposed techniques into fpga design automation flow is discussed and experimental results are presented.
This work describes an intensive investigation on the test strategy known as polynomial fitting that uses fpga generated stimuli for cheap and fast testing of high resolution ADCs. Simulation and experimental results ...
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ISBN:
(纸本)0769525237
This work describes an intensive investigation on the test strategy known as polynomial fitting that uses fpga generated stimuli for cheap and fast testing of high resolution ADCs. Simulation and experimental results showed a sensitivity on the specifications parameters detection of 90dB. The proposed method can also help to control the cost of ADC production test, extends the test coverage and enable built-in self-test and test-based self-calibration.
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