In this paper we propose a dual-Vt fpga architecture for reduction of subthreshold leakage power A CAD flow has been proposed based on the dual-Vt assignment algorithm and placement for realizing the dual-Vt fpga arch...
详细信息
ISBN:
(纸本)0769525237
In this paper we propose a dual-Vt fpga architecture for reduction of subthreshold leakage power A CAD flow has been proposed based on the dual-Vt assignment algorithm and placement for realizing the dual-Vt fpga architecture. Logic elements within the logic blocks are the candidates for dual-Vt assignment. We propose an architecture in which there are two kinds of logic blocks, one with all high-Vt logic elements and another with a fixed percentage of high-Vt logic elements. These two kinds of logic blocks are then placed in such a way that the fpga architecture remains regular Results indicate that in the ideal case of dual-Vt assignment, over 95% of the logic elements can be assigned high-Vt. Results show that leakage savings of 55% can be achieved. Design tradeoffs for various ratios of the two kinds of logic blocks are investigated. The dual-Vt fpga CAD flow is intended for development and evaluation of dual-Vt fpga architectures.
The proceedings contains 24 papers from the acm/sigdainternationalsymposium on fieldprogrammablegatearrays - fpga 2004. The topics discussed include: exploration of pipelined fpga interconnect structures;evaluati...
详细信息
The proceedings contains 24 papers from the acm/sigdainternationalsymposium on fieldprogrammablegatearrays - fpga 2004. The topics discussed include: exploration of pipelined fpga interconnect structures;evaluation of low leakage design techniques for fieldprogrammablegatearrays;reducing leakage energy in fpgas using region constrained placement;an embedded true random number generator for fpgas;a synthesis oriented omniscient manual editor;nanowire-based sublithographic programmable logic arrays;and highly pipelined asynchronous fpgas.
Multi-point distributed random variables whose moments match those of a Gaussian random variable up to a certain order play an important role in Monte Carlo simulations of weak approximations of stochastic differentia...
详细信息
Multi-point distributed random variables whose moments match those of a Gaussian random variable up to a certain order play an important role in Monte Carlo simulations of weak approximations of stochastic differential equations. In applications such as finance, where "real time" execution is required, there is a strong need for highly efficient implementations. In this paper a fast and flexible dedicated hardware solution on a fieldprogrammablegate Array (fpga) is presented. A comparative performance analysis between a software-only and the proposed hardware solution demonstrates that the fpga solution is bottleneck-free, retains the flexibility of the software solution and significantly increases the computational efficiency.
In this paper we study the effect of post-layout pin permutation of designs for fpga devices with non-uniform cell delays. We present a simple, but timing optimal, pin permutation scheme, and report the results of app...
详细信息
ISBN:
(纸本)9781595930293
In this paper we study the effect of post-layout pin permutation of designs for fpga devices with non-uniform cell delays. We present a simple, but timing optimal, pin permutation scheme, and report the results of applying the scheme on a set of public logic synthesis benchmark designs that were synthesized and placed by state-of-the-art commercial fpga design tools configured to maximum optimization level. Despite the preceding optimizations, we still observed an average timing improvement of 3.7%. This demonstrates the importance of fully utilizing non-uniform cell delays during design optimizations for modern fpga devices and the still presenting potential of improvement. Copyright 2005 acm.
This article is a concise literature review of the actual state of the art in arithmetic for field-programmablegatearrays (fpgas), including studies, implementation techniques, operators, and structures, in various ...
详细信息
This article is a concise literature review of the actual state of the art in arithmetic for field-programmablegatearrays (fpgas), including studies, implementation techniques, operators, and structures, in various area-time tradeoffs. It covers the integer operations of addition/subtraction, multiplication, squaring, division, and square root, in parallel, and in both serial modes (least-significant digit first, and online). Many people, including researchers in the field of computer arithmetic, parallel computing, digital signal and image processing, system-on-a-programmable chip (SoPC) designers, and other people with a need to implement special purpose arithmetic circuits on fpgas, might find such a review useful, either as an introduction to the topic, as a knowledge update, or for reference.
This paper discusses architectural issues arising from the use of dynamic reconfiguration and shows a possible use of dynamic reconfiguration to extend and accelerate a computation performed in system-on-a-chip design...
详细信息
This paper discusses architectural issues arising from the use of dynamic reconfiguration and shows a possible use of dynamic reconfiguration to extend and accelerate a computation performed in system-on-a-chip designs with microprocessors with fixed instruction sets. Further a sample application is discussed that uses a dynamically reconfigurable fpga to implement different floating-point calculations in hardware, reconfigured as required by the execution of the user code. The implementation data for two dynamically reconfigurable platforms available on the market - the Xilinx Virtex2 family fpgas and the Atmel FPSLIC family fpgas - is compared in terms of resource requirements, operating frequency, and power consumption.
fpga-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs. Soft error rate (SER) estimation is a crucial step in the design of soft error tolerant schemes to balance reliability, p...
详细信息
ISBN:
(纸本)9781595930293
fpga-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs. Soft error rate (SER) estimation is a crucial step in the design of soft error tolerant schemes to balance reliability, performance, and cost of the system. Previous techniques on fpga SER estimation are based on time-consuming fault injection and simulation methods. In this paper, we present an analytical approach to estimate the failure rate of designs mapped into fpgas. Experimental results show that this technique is orders of magnitude faster than fault injection method while is very accurate. We also present a high-reliable low-cost mitigation technique which can significantly improve the availability of fpga-based designs. This technique is able to tolerate SEUs in both user and configuration bits of mapped designs. Copyright 2005 acm.
This paper presents an analysis of the potential yield loss in fpga due to random defects in metal layers. A proven yield model is adapted to target the fpga interconnect layers in order to predict the manufacturing y...
详细信息
ISBN:
(纸本)9781595930293
This paper presents an analysis of the potential yield loss in fpga due to random defects in metal layers. A proven yield model is adapted to target the fpga interconnect layers in order to predict the manufacturing yield. Defect parameters from the 2003 SIA roadmap are used to investigate the trend in yield loss due to defects in interconnect layers in the future. It is shown that the low yield predicted for the 45nm technology node and beyond is a cause for concern. The potential impact on yield using two different approaches, namely redundant circuits and fault tolerant design, is also presented. Copyright 2005 acm.
Advanced Microelectronics Department at Sandia National Laboratories. We present an automatic logic synthesis method targeted for high-performance asynchronous fpga (Afpga) architectures. Our method transforms sequent...
详细信息
ISBN:
(纸本)9781595930293
Advanced Microelectronics Department at Sandia National Laboratories. We present an automatic logic synthesis method targeted for high-performance asynchronous fpga (Afpga) architectures. Our method transforms sequential programs as well as high-level descriptions of asynchronous circuits into fine-grain asynchronous process netlists suitable for an Afpga. The resulting circuits are inherently pipelined, and can be physically mapped onto our Afpga with standard partitioning and place-and-route algorithms. For a wide variety of benchmarks, our automatic synthesis method not only yields comparable logic densities and performance to those achieved by hand placement, but also attains a throughput close to the peak performance of the fpga. Copyright 2005 acm.
Even with HiCuts algorithm, which is one of the most effective algorithms for packet classification, the on-line searching for each input packet still consumes the main CPU a large amount of computation resource if it...
详细信息
ISBN:
(纸本)9781595930293
Even with HiCuts algorithm, which is one of the most effective algorithms for packet classification, the on-line searching for each input packet still consumes the main CPU a large amount of computation resource if it is fulfilled by software. An effective alternative is to use a hardware co-processor to realize the on-line searching. Based on the principle of HiCuts algorithm, the architecture design of a hardware on-line searching co-processor with an fpga is presented in this paper. Especially, mapping the decision tree and linear search in each leaf node to the memory data structure is described in detail. Benefiting from multiple pipeline structure, there are a total of 12 searching engines working parallel to achieve very high searching speed (8M packet heads/second). The simulation test results show a useful guide for optimization of off-line pre-processing and the co-processor design.
暂无评论