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检索条件"任意字段=2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013"

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Efficient utilization of heterogeneous routing resources for fpgas

Efficient utilization of heterogeneous routing resources for...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - fpga 2005

作者： Rautela, Deepak Katti, Rajendra Department of Electrical and Computer Engineering North Dakota State University Fargo ND 58105

The routing resources available in recent fpga architectures (e.g., Xilinx Virtex-II) are very different from the older generation of fpgas (e.g., Xilinx XC4000). The latest fpga architectures have heterogeneous routing resources which include directly driven wires of different lengths and connectivity. Most of the fpga routing algorithms have been implemented on XC4000 style architectures and not much work has been reported for architectures with directly driven heterogeneous routing resources. Since routing resources in fpgas are fixed, it is very important for the routing algorithms to fully exploit the potential of new routing architectures. fpga routing architectures are usually represented as a routing resource graph (RRG). The construction of RRG to accurately model all the routing resources of current fpga architectures is not a trivial task. In this paper we present a simplified scheme to build the RRG for fpga architectures with heterogeneous routing resources. Using our RRG construction scheme we have built a routability driven detailed fpga router named "Bison". We also present a dynamic weight update based heuristic which we have incorporated into the router, so that efficient utilization of routing resources can be achieved.

关键词： field programmable gate arrays

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Hyper customized processors for bio-sequence database scanning on fpgas 05

Hyper customized processors for bio-sequence database scanni...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - fpga 2005

作者： Oliver, Tim Schmidt, Bertil Maskell, Douglas Centre for High Performance Embedded Systems Nanyang Technological University Singapore Singapore

ISBN: (纸本)9781595930293

Protein sequences with unknown functionality are often compared to a set of known sequences to detect functional similarities. Efficient dynamic-programming algorithms exist for solving this problem, however current solutions still require significant scan times. These scan time requirements are likely to become even more severe due to exponential database growth. In this paper we present a new approach to bio-sequence database scanning using re-configurable fpga-based hardware platforms to gain high performance at low cost. Efficient mappings of the Smith-Waterman algorithm using fine-grained parallel processing elements (PEs) that are tailored towards the parameters of a query have been designed. We use customization opportunities available at run-time to dynamically hyper customize the systolic array to make better use of available resource. Our fpga implementation achieves a speedup of approximately 170 for linear gap penalties and 125 for affine gap penalties as compared to a standard desktop computing platform. We show how hyper-customization at run-time can be used to further improve the performance. Copyright 2005 acm.

关键词： field programmable gate arrays

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Combining low-leakage techniques for fpga routing design 05

Combining low-leakage techniques for FPGA routing design

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - fpga 2005

作者： Lodi, Andrea Ciccarelli, Luca Giansante, Roberto ARCES University of Bologna Bologna Italy

ISBN: (纸本)9781595930293

Reconfigurable architectures are well suited for wireless applications since they provide high performance computation together with the capability to adapt to changing communication protocols. Moving to 90nm technology and below, fpgas could suffer from leakage energy consumption due to the large number of inactive transistors. We propose to combine super cut-off, body biasing and multi-threshold techniques to reduce the leakage current of programmable interconnections, which give by far the main contribution to static power dissipation. Super cut-off (gate biasing) technique is well suited for high-speed pass-transistors, while body biasing can be adopted for large buffers. On the other hand high threshold transistors can be used where delays are not critical. We show the design of SRAM cells generating the required high swing signals for gate-biased and body-biased transistors without affecting transistor reliability. Compared to a standard design the adoption of a mixed technique reduces routing leakage by more than one order of magnitude with only a 5% increase in switch delay and a 9% in tile area, while with respect to a full dual-threshold approach, delay is reduced by 23%. Copyright 2005 acm.

关键词： field programmable gate arrays

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Soft multiprocessor systems for network applications

Soft multiprocessor systems for network applications

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - fpga 2005

作者： Jin, Yujia Plishker, William Ravindran, Kaushik Satish, Nadathur Keutzer, Kurt Electrical Engineering and Computer Sciences UC Berkeley Berkeley CA 94709

Modem network applications require devices that provide high-performance at gigabit line rates with the flexibility to support diverse application standards and services. However, prohibitive product design costs and shrinking market windows restrict the number of ASIC/ASSP design starts to only selective application niches. The fpga is an alternate cost-effective medium for many applications. However, creating a system solution through programming an fpga with an HDL is only attractive to few application developers. Designers would prefer a software solution if it can meet their design constraints. An alterative is an fpga-based soft multiprocessor system: a programmable multiprocessor on the fpga composed of a network of hard and soft processing cores. Soft multiprocessors provide a software-level abstraction for programming an fpga. In this study, we evaluate the feasibility and effectiveness of soft multiprocessor systems. We compare a soft multiprocessor implementation against fpga hardware and an ASSP implementation for two network applications: IPv4 packet forwarding and Network Address Translation (NAT). Our study indicates that soft multiprocessors lose only a factor of 2X in performance compared to a custom ASSP, while providing great savings in terms of silicon development costs. Moreover, the presence of architectures and development environments for soft multiprocessor systems could open the fpga market to the much larger world of embedded system software designers.

关键词： field programmable gate arrays

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Efficient methodology for detection and correction of SEU-based interconnect errors in fpgas using partial reconfiguration

Efficient methodology for detection and correction of SEU-ba...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - fpga 2005

作者： Reddy, E. Syam Sundar Chandrasekhar, Vikram Sashikanth, M. Kamakoti, V. Narayanan, Vijaykrishnan Dept. of Computer Science and Engineering Indian Institute of Technology Madras Chennai - 600036 India Department of Computer Science and Engineering Pennsylvania State University University Park PA 16802 United States

This paper proposes a new CLB architecture for fpgas and associated testing and reconfiguration techniques that detect single routing/interconnect errors and correct them using partial reconfiguration. The results of error detection are propagated to a single output port by a chain-like shift register, which are used to reduce the segment of the routing architecture that has to be reconfigured. The error is corrected by partially reconfiguring the above minimal segment alone, thereby reducing the time for reconfiguration. The proposed testing technique detects all possible routing errors that affects the logic of the circuit, including bridging faults. It is noteworthy that the time required for error detection is independent of both the number of switch matrices and the number of logic blocks in the fpga. Empirically, our technique detected all single interconnect errors in benchmark circuits. In addition, for the majority of errors, our correction technique required less than 10% of the switch matrices to be reconfigured to correct the errors.

关键词： field programmable gate arrays

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Skew-programmable clock design for fpga and skew-aware placement 05

Skew-programmable clock design for FPGA and skew-aware place...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - fpga 2005

作者： Yeh, Chao-Yang Marek-Sadowska, Malgorzata ECE Department University of California Santa Barbara CA 93106 United States

ISBN: (纸本)9781595930293

In this paper, we propose a skew-programmable clock-routing architecture. The skews can be adjusted using programmable delay elements (PDEs) which we insert into the clock trees. We develop efficient, shortest-path-based algorithms for programming PDEs to optimize timing. Unlike previous methods for fpga skew optimization which require large power and routing penalty, our method can achieve large timing improvement with small overhead. Typically, if timing requirements are tight, placers make efforts to satisfy them, often at a cost of compromising routability, total wire length, and power. In this work, we propose novel clock-skew-aware placement algorithms which allow us to relax the timing constraints during placement. Timing can be later optimized as a post process. Even though we demonstrate the efficiency of our approach using fpgas, the new skew optimization method and the new placement algorithm are quite general and can be applied to any general, topology-constrained skew optimization problem. Experimental results indicate that using the new clock-architecture we can obtain a 22% timing improvement for post-layout skew optimization and an additional 21% improvement from our skew-aware placement algorithm. In one fabric, the cost of added logic is 2.19% as measured by dynamic power dissipation, and 0.85% in terms of area overhead. Copyright 2005 acm.

关键词： field programmable gate arrays

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64-bit floating-point fpga matrix multiplication 05

64-bit floating-point FPGA matrix multiplication

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - fpga 2005

作者： Dou, Yong Vassiliadis, S. Kuzmanov, G.K. Gaydadjiev, G.N. National Laboratory for Parallel and Distributed Processing Changsha 410073 China Computer Engineering EEMCS TU Delft P.O. Box 5031 2600 GA Delft Netherlands

ISBN: (纸本)9781595930293

We introduce a 64-bit ANSI/IEEE Std 754-1985 floating point design of a hardware matrix multiplier optimized for fpga implementations. A general block matrix multiplication algorithm, applicable for an arbitrary matrix size is proposed. The algorithm potentially enables optimum performance by exploiting the data locality and reusability incurred by the general matrix multiplication scheme and considering the limitations of the I/O bandwidth and the local storage volume. We implement a scalable linear array of processing elements (PE) supporting the proposed algorithm in the Xilinx Virtex II Pro technology. Synthesis results confirm a superior performance-area ratio compared to related recent works. Assuming the same fpga chip, the same amount of local memory, and the same I/O bandwidth, our design outperforms related proposals by at least 1.7X and up to 18X consuming the least reconfigurable resources. A total of 39 PEs can be integrated into the xc2vp125-7 fpga, reaching performance of, e.g., 15.6 GFLOPS with 1600 KB local memory and 400 MB/s external memory bandwidth. Copyright 2005 acm.

关键词： field programmable gate arrays

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CUSP: A modular framework for high speed network applications on fpgas

CUSP: A modular framework for high speed network application...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - fpga 2005

作者： Schelle, Graham Grunwald, Dirk Computer Science University of Colorado at Boulder Boulder CO

For several years now, modern fpgas have included onchip network related hard cores. These cores include Xilinx's RocketIO and Altera's RapidIO serial transceivers. However, to use these cores in a complete networking application may be a daunting task to a non-networking expert. In addition to the complicated use of these components, the high performance needs of modern networking applications require designs that are optimized for low latency and a moderately high clock rate. Therefore to meet these challenges, we present CUSP (Click Utilizing Speculation and Parallelism) for reconfigurable hardware platforms. Click is an accepted software network router framework that is similar to CUSP, but specifically built for a Linux platform and software network routers. CUSP, while also having a modular design of reusable components, additionally provides automated speculation and parallelism to gain better performance on fpgas. An accompanying scripting language allows quick creation of these routers from a body of existing components. We have implemented an example network application through the CUSP design flow and its performance will be compared against alternative network design methods. Copyright 2005 acm.

关键词： field programmable gate arrays

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Domain specific non-uniform routing architecture for embedded programmable IP core 05

Domain specific non-uniform routing architecture for embedde...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - fpga 2005

作者： Wen, Yujie Tong, Jiarong Chiang, Charles State Key Lab of ASIC and System Fudan University Shanghai China Synopsys Inc. Mountain View CA 94043

ISBN: (纸本)9781595930293

Non-uniform routing architecture contains routing channels of different widths. In this paper we propose a design methodology of domain specific non-uniform programmable routing architecture for embedded programmable IP cores. This non-uniform architecture is based on symmetrical fpga model and consists of connection boxes of full connectivity and rectangular switch boxes. The rectangular switch box is derived from universal switch box module. Area and timing efficiency of the proposed architecture is compared with those of uniform architecture based on placement and routing result over a set of MCNC benchmark circuits. The comparison results show that non-uniform routing architecture gains up to 8% layout area reduction from uniform ones. Besides, by widening some of the routing channels where routing congestions accumulate, the average critical path delay of non-uniform architecture is 8% less than that of uniform one while maintain the same area.

关键词： Embedded systems

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3D fpgas: Placement, routing, and architecture evaluation

3D FPGAs: Placement, routing, and architecture evaluation

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - fpga 2005

作者： Ababei, Cristinel Mogal, Hushrav Bazargan, Kia Department of Electrical and Computer Engineering University of Minnesota Minneapolis MN 55455

This paper introduces a novel 3-Dimensional (3D) vertically integrated adaptive computing system. This 3D-SoftChip is a combination of state-of-the-art processing and interconnection technology. It comprises the vertical integration of two chips (a Configurable Array Processor and an Intelligent Configurable Switch) through indium bump 3D interconnections. The Configurable Array Processor (CAP) is an array of heterogeneous processing elements (PEs) while the Intelligent Configurable Switch (ICS) comprises a switch block, 32-bit dedicated RISC processor for control, on-chip program/data memory, data frame buffer along with a Direct Memory Access (DMA) controller. This paper introduces the 3D-Softchip architecture for real-time communication and multimedia signal processing as a next gene! ration computing system. The paper further describes the up-to-date HW/SW co-design and verification methodology including high level system modeling and architecture exploration of 3D-SoftChip using SystemC in order to determine the optimum hardware specification in the early design stage.

关键词： field programmable gate arrays

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