How does multilevel metalization impact the design of fpga interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the third-dimension to reduce switch requirements...
详细信息
How does multilevel metalization impact the design of fpga interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the third-dimension to reduce switch requirements. Unfortunately, traditional fpga wiring schemes are not designed to exploit these additional metal layers. We introduce an alternate topology, based on Leighton's Mesh-of-Trees, which carefully exploits hierarchy to allow additional metal layers to support arbitrary device scaling. When wiring layers grow sufficiently fast with aggregate network size (N), our network requires only O(N) area: this is in stark contrast to traditional. Manhattan fpga routing schemes where switching requirements alone grow superlinearly in N. In practice, we show that, even for the admittedly small designs in the Toronto "fpga Place and Route Challenge," the Mesh-of-Trees networks require 10% less switches than the standard, Manhattan fpga routing scheme.
In recent years the challenge of high performance, low power retargettable embedded system has been faced with different technological and architectural solutions. In this paper we present a new configurable unit expl...
详细信息
In recent years the challenge of high performance, low power retargettable embedded system has been faced with different technological and architectural solutions. In this paper we present a new configurable unit explicitly designed to implement additional reconfigurable pipelined datapaths, suitable for the design of reconfigurable processors. A VLIW reconfigurable processor has been implemented on silicon in a standard 0.18 μm CMOS technology to prove the effectiveness of the proposed unit. Testing on a signal processing algorithms benchmark showed speedups from 4.3x to 13.5x and energy consumption reduction up to 92%.
Though verification is significantly easier for fpga-based digital systems than for ASIC or full-custom hardware, there are nonetheless many places for errors to occur. In this paper we discuss the verification proble...
详细信息
Though verification is significantly easier for fpga-based digital systems than for ASIC or full-custom hardware, there are nonetheless many places for errors to occur. In this paper we discuss the verification problem for fpgas and describe several methods for verifying end-to-end correctness of synthesis algorithms, a particularly complex portion of the CAD flow. Though the primary contribution of this paper is the analysis of the overall problem, we also give an algorithm for the automatic generation of test-vectors for simulation using information from the synthesis tool, and describe a second testing method that generates purposefully difficult designs in combination with input vectors to test them. We will show the validity of these methods by standard metrics such as simulation node-coverage and through the ability for the method to locate forced errors introduced by the synthesis tool.
This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based fpgas, without modifications in the fpga architecture. Traditionally, TMR has been successfully applied in fpgas to mit...
详细信息
This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based fpgas, without modifications in the fpga architecture. Traditionally, TMR has been successfully applied in fpgas to mitigate transient faults, which are likely to occur in space applications. However. TMR comes with high area and power dissipation penalties. The proposed technique was specifically developed for fpgas to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power dissipation. The methodology was validated by fault injection experiments in an emulation board. We present some fault coverage results and a comparison with the TMR approach.
In this paper, we present the first exact algorithm to solve the constrained I/O placement problem for fpgas that support multiple I/O standards. We derive a compact integer linear programming formulation for the cons...
详细信息
In this paper, we present the first exact algorithm to solve the constrained I/O placement problem for fpgas that support multiple I/O standards. We derive a compact integer linear programming formulation for the constrained I/O placement problem. The size of the integer linear program derived is independent of the number of I/O objects to be placed and hence is scalable to very large design instances. For example, for a Xilinx Virtex-E fpga, the number of integer variables required is never more than 32 and is much smaller for practical design instances. Extensive experimental results using a non-commercial integer linear program solver shows that it only takes seconds to solve the resultant integer linear program in practice.
This paper presents a flexible fpga architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based fpga architectures. Our work has several contributions: (i) We develop a mixed-level ...
详细信息
This paper presents a flexible fpga architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based fpga architectures. Our work has several contributions: (i) We develop a mixed-level fpga power model that combines switch-level models for interconnects and macromodels for LUTs;(ii) We develop a tool that automatically generates a back-annotated gate-level netlist with post-layout extracted capacitances and delays;(iii) We develop a cycle-accurate power simulator based on our power model. It carries out gate-level simulation under real delay model and is able to capture glitch power;(iv) Using the frame work fpgaEVA-LP, we study the power efficiency of fpgas, in 0.10um technology, under various settings of architecture parameters such as LUT sizes, cluster sizes and wire segmentation schemes and reach several important conclusions. We also present the detailed power consumption distribution among different fpga components and shed light on the potential opportunities of power optimization for future fpga designs (e.g., ≤ 0.10um technology).
The purpose of this paper is to introduce a modified packing and placement algorithm for fpgas that utilizes logic duplication to improve performance. The modified packing algorithm was designed to leave unused basic ...
详细信息
The purpose of this paper is to introduce a modified packing and placement algorithm for fpgas that utilizes logic duplication to improve performance. The modified packing algorithm was designed to leave unused basic logic elements (BLEs) in timing critical clusters, to allow potential targets for logic duplication. The modified placement algorithm consists of a new stage after placement in which logic duplication is performed to shorten the length of the critical path. In this paper, we show that in a representative fpga architecture using .18 μm technology, the length of the final critical path can be reduced by an average of 14.1%. Approximately half of this gain comes directly from the changes to the packing algorithm while the other half comes from the logic duplication performed during placement.
To truly exploit fpgas for rapid turn-around development and prototyping, placement times must be reduced to seconds;late-bound, reconfigurable computing applications may demand placement times as short as microsecond...
详细信息
To truly exploit fpgas for rapid turn-around development and prototyping, placement times must be reduced to seconds;late-bound, reconfigurable computing applications may demand placement times as short as microseconds. In this paper, we show how a systolic structure can accelerate placement by assigning one processing element to each possible location for an fpga LUT from a design netlist. We demonstrate that our technique approaches the same quality point as traditional simulated annealing as measured by a simple linear wirelength metric. Experimental results look ahead to compare quality against VPR's fast placer when considering the minimum channel width required to route as the primary optimization criteria. Preliminary results from an fpga implementation show the feasibility of accelerating simulated annealing by three orders of magnitude using this approach. This means we can place the largest design in the University of Toronto's "fpga Placement and Routing Challenge" in around 4ms.
This paper presents a new power saving, high speed fpga design enhancing a previous SiGe CML fpga based on the Xilinx 6200 fpga. The design aims at having a higher performance but minimizing power consumption. The new...
详细信息
This paper presents a new power saving, high speed fpga design enhancing a previous SiGe CML fpga based on the Xilinx 6200 fpga. The design aims at having a higher performance but minimizing power consumption. The new SiGe process has traded off the circuit's performance for reduced power consumption. The power supply voltage has been reduced from 3.4 V to 2.0 V. The structure of the Basic Cell, including the Configurable Logic Block (CLB) and routing multiplexers (MUXs), has been modified so that the supply voltage reduction can be attained. Simulations have shown that the gate delay of the new Basic Cell is reduced from 130 ps in the prior design to 51 ps. The total power consumption for each Basic Cell has been reduced 94% from 71 mW to 4.2 mW. making a large scale fpga feasible. This design is currently under fabrication for testing.
This paper describes the hardware implementation of a real-time, large-scale, multi-chip fpga (fieldprogrammablegate Array) based emulation engine with a capacity of 10 million ASIC (Application Specific Integrated ...
详细信息
This paper describes the hardware implementation of a real-time, large-scale, multi-chip fpga (fieldprogrammablegate Array) based emulation engine with a capacity of 10 million ASIC (Application Specific Integrated Circuits) equivalent gates. Attainable system operation frequency can exceed 60 MHz, and the system throughput has been empirically verified to achieve 600 billion 16-bit additions per second. The emulator is custom designed to maximize the performance and resource utilization for a range of telecommunication and digital signal processing applications. With its high-speed interconnect architecture and large external I/O bandwidth, the emulator excels in prototyping real-time systems that have strict timing, logic capacity, and data rate requirements. Our development efforts are guided by such ongoing projects as ultra-wide band (UWB) and multi-channel-multi-antenna (MCMA) radio systems research.
暂无评论