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检索条件"任意字段=2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013"

共 809 条记录，以下是61-70 订阅

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A scalable and robust hierarchical floorplanning to enable 24-hour prototyping for 100k-LUT fpgas 21

A scalable and robust hierarchical floorplanning to enable 2...

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2021 acm international symposium on Physical Design, ISPD 2021

作者： Gore, Ganesh Tang, Xifan Gaillardon, Pierre-Emmanuel University of Utah Salt Lake CityUT United States

ISBN: (纸本)9781450383004

Physical design for field programmable gate Array (fpga) is challenging and time-consuming, primarily due to the use of a full-custom approach for aggressively optimize Performance, Power and Area (P.P.A.) of the fpga design. The growing number of fpga applications demands novel architectures and shorter development cycles. The use of an automated toolchain is essential to reduce end-to-end development time. This paper presents scalable and adaptive hierarchical floorplanning strategies to significantly reduce the physical design runtime and enable millions-of-LUT fpga layout implementations using standard ASIC toolchains. This approach mainly exploits the regularity of the design and performs necessary feedthrough creations for global and clock nets to eliminate any requirement of global optimizations. To validate this approach, we implemented full-chip layouts for modern fpga fabric with logic capacity ranging from 40 to 100k LUTs using a commercial 12nm technology. Our results show that the physical implementation of a 128k-LUT fpga fabric can be achieved within 24-hours, which has not been demonstrated by any previous work. Compared to previous work, the runtime reduction of 8x is obtained for implementing 2.5k LUTs fpga device. © 2021 acm.

关键词： field programmable gate arrays (fpga)

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Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of programmable Routing 20

Straight to the Point: Intra- and Intercluster LUT Connectio...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Nikolic, Stefan Zgheib, Grace Ienne, Paolo Ecole Polytech Fed Lausanne EPFL Lausanne Switzerland Intel Corp San Jose CA USA

ISBN: (纸本)9781450370998

Technology scaling makes metal delay ever more problematic, but routing between Look-Up Tables (LUTs) still passes through a series of transistors. It seems wise to avoid the corresponding delay whenever possible. Direct connections between LUTs, both within and across multiple clusters, can eschew the transistor delays of crossbars, connection blocks, and switch blocks. In this paper we investigate the usefulness of enhancing classical field-programmable gate Array (fpga) architectures with direct connections between LUTs. We present an efficient algorithm for searching automatically the most interesting patterns of such direct connections. Despite our methods being fairly conservative and relying on the use of unmodified standard CAD tools, we obtain a 2.77% improvement of the geometric mean critical path delay of a standard benchmark set, with improvement ranging from -0.17% to 7.3% for individual circuits. As modest as these results may seem at first glance, we believe that they position direct connections between LUTs as a promising topic for future research. Extending this work with dedicated CAD algorithms and exploiting the increased possibilities for optimal buffering, diagonal routing, and pipelining could prove direct connections important to the continuation of performance improvement into next generation fpgas.

关键词： intercluster architectural exploration fpga lut cluster interconnect pattern direct connection clb hardened connection search intracluster enumeration algorithm

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HMLib: Efficient Data Transfer for HLS Using Host Memory 23

HMLib: Efficient Data Transfer for HLS Using Host Memory

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Proceedings of the 2023 acm/sigda international symposium on field programmable gate arrays

作者： Michael Lo Young-kyu Choi Weikang Qiao Mau-Chung Frank Chang Jason Cong University of California Los Angeles Los Angeles CA USA Inha University Incheon Republic of Korea

ISBN: (纸本)9781450394178

Streaming applications compose an important portion of the workloads that fpgas may accelerate but suffer from inefficient data movement. The inefficiency stems from copying data indirectly into the fpga DRAM rather than directly into its on-chip memory, substantially diminishing the end-to-end speedup, especially for small workloads (hundreds of kilobytes). AMD Xilinx's Host Memory IP (HMI) aims to address the data movement problem by exposing to the developer an High-Level Synthesis (HLS) interface that moves the data from the host directly to the fpga's on-chip memory. However, using HMI purely for its interface without additional code changes incurred a 3.3x slowdown in comparison with the current programming model. The slowdown mainly originates from OpenCL call overhead and the kernel control logic unnecessarily switching states. To overcome these issues, we propose Host Memory Library (HMLib), an efficient HLS-based library that facilitates data transfer on behalf of the user. HMLib not only optimizes the runtime stack for efficient data transfer, but also provides HLS compatible and user-friendly interfaces. We demonstrate HMLib's effectiveness for streaming applications (Deflate compression and CRC32) with improvements of up to up to 36.2X over OpenCL-DDR and up to 79.5X over raw HMI for small-scale data while maintaining little-to-no performance loss for large scale inputs. We plan to open source our work in the future.

关键词： high-level synthesis field-programmable gate array on-chip memory host memory opencl streaming workload

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A Flexible Toolflow for Mapping CNN Models to High Performance fpga-based Accelerators 23

A Flexible Toolflow for Mapping CNN Models to High Performan...

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Proceedings of the 2023 acm/sigda international symposium on field programmable gate arrays

作者： Yongzheng Chen Gang Wu Northeastern University Shenyang China

ISBN: (纸本)9781450394178

There have been many studies on developing automatic tools for mapping CNN models onto fpgas. However, challenges remain in designing an easy-to-use toolflow. First, the toolflow should be able to handle models exported from various deep learning frameworks and models with different topologies. Second, the hardware architecture should make better use of on-chip resources to achieve high performance. In this work, we build a toolflow upon Open Neural Network Exchange (ONNX) IR to support different DL frameworks. We also try to maximize the overall throughput via multiple hardware-level efforts. We propose to accelerate the convolution operation by applying parallelism not only at the input and output channel level, but also at the output feature map level. Several on-chip buffers and corresponding management algorithms are also designed to leverage abundant memory resources. Moreover, we employ a fully pipelined systolic array running at 400 MHz as the convolution engine, and develop a dedicated bus to implement the im2col algorithm and provide feature inputs to the systolic array. We generated 4 accelerators with different systolic array shapes and compiled 12 CNN models for each accelerator. Deployed on a Xilinx VCU118 evaluation board, the performance of convolutional layers can reach 3267.61 GOPS, which is 99.72% of the ideal throughput (3276.8 GOPS). We also achieve an overall throughput of up to 2424.73 GOPS. Compared with previous studies, our toolflow is more user-friendly. The end-to-end performance of the generated accelerators is also better than that of related work at the same DSP utilization.

关键词： field-programmable gate array (fpga) toolflow convolutional neural network (CNN) systolic array memory management

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LUXOR: An fpga logic cell architecture for eficient compressor tree implementations

LUXOR: An FPGA logic cell architecture for eficient compress...

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2020 acm/sigda international symposium on field-programmable gate arrays, fpga 2020

作者： Rasoulinezhad, Seyed Ramin Siddhartha Zhou, Hao Wang, Lingli Boland, David Leong, Philip H.W. School of Electrical and Information Engineering University of Sydney Sydney2006 Australia State Key Lab of ASIC and System Fudan University Shanghai201203 China

ISBN: (纸本)9781450370998

We propose two tiers of modiications to fpga logic cell architecture to deliver a variety of performance and utilization beneits with only minor area overheads. In the irst tier, we augment existing commercial logic cell datapaths with a 6-input XOR gate in order to improve the expressiveness of each element, while maintaining backward compatibility. This new architecture is vendor-agnostic, and we refer to it as LUXOR. We also consider a secondary tier of vendor-speciic modiications to both Xilinx and Intel fpgas, which we refer to as X-LUXOR+ and I-LUXOR+ respectively. We demonstrate that compressor tree synthesis using generalized parallel counters (GPCs) is further improved with the proposed modiications. Using both the Intel adaptive logic module and the Xilinx slice at the 65nm technology node for a comparative study, it is shown that the silicon area overhead is less than 0.5% for LUXOR and 5-6% for LUXOR+, while the delay increments are 1-6% and 3-9% respectively. We demonstrate that LUXOR can deliver an average reduction of 13-19% in logic utilization on micro-benchmarks from a variety of *** benchmarks beneit the most with an average reduction of 37-47% in logic utilization, which is due to the highly-eicient mapping of the XnorPopcount operation on our proposed LUXOR+ logic cells. © 2020 Association for Computing Machinery.

关键词： field programmable gate arrays (fpga)

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fpga 2016 - Proceedings of the 2016 acm/sigda international symposium on field-programmable gate arrays

FPGA 2016 - Proceedings of the 2016 ACM/SIGDA International ...

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2016 acm/sigda international symposium on field-programmable gate arrays, fpga 2016

ISBN: (纸本)9781450338561

The proceedings contain 32 papers. The topics discussed include: hyperpipelining of high-speed interface logic;agile co-design for a reconfigurable datacenter;throughput-optimized OpenCL-based fpga accelerator for large-scale convolutional neural networks;going deeper with embedded fpga platform for convolutional neural network;using stochastic computing to reduce the hardware requirements for a restricted Boltzmann machine classifier;a platform-oblivious approach for heterogeneous computing: a case study with Monte Carlo-based simulation for medical applications;physical design of 3D fpgas embedded with micro-channel-based fluidic cooling;Boolean satisfiability-based routing and its application to Xilinx ultrascale clock network;and pitfalls and tradeoffs in simultaneous, on-chip fpga delay measurement.

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A Four-Phase Self-Timed Ring Based True Random Number Generator on fpga 16

A Four-Phase Self-Timed Ring Based True Random Number Genera...

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16th IEEE international Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022

作者： Gu, Haoang Deng, Fangyu Wang, Qin Jing, Naifeng Jiang, Jianfei Yao, Gang Zhou, Lidan Shanghai Jiao Tong University School of Electronic Information and Electrical Engineering Shanghai200240 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

The random number generators (TRNGs) provide unpredictable data for various encryption operations such as information security. In this paper, a novel structure of TRNG is proposed based on the random jitter of a four-phase self-timed ring (FPSTR) as the entropy source on fpga. The proposed TRNG is implemented on Xilinx KCU116 fpgas with high throughput. Compared with existing designs, our proposal occupies 324 LUTs and 62 DFFs, and its throughput is up to 200 Mbps. The random bitstream generated by TRNG is statistically tested and passes the NIST SP800-22 and the NIST SP800-90B test. © 2022 IEEE.

关键词： field programmable gate arrays (fpga)

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Extending High-Level Synthesis for Task-Parallel Programs 21

Extending High-Level Synthesis for Task-Parallel Programs

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The 2021 acm/sigda international symposium on field-programmable gate arrays

作者： Yuze Chi Licheng Guo Young-kyu Choi Jie Wang Jason Cong University of California Los Angeles Los Angeles CA USA

ISBN: (纸本)9781450382182

C/C++/OpenCL-based high-level synthesis (HLS) becomes more and more popular for field-programmable gate array (fpga) accelerators in many application domains in recent years, thanks to its competitive quality of result (QoR) and short development cycle compared with the traditional register-transfer level (RTL) design approach. Yet, limited by the sequential C semantics, it remains challenging to adopt the same highly productive high-level programming approach in many other application domains, where coarse-grained tasks run in parallel and communicate with each other at a fine-grained level. While current HLS tools support task-parallel programs, the productivity is greatly limited in the code development, correctness verification, and QoR tuning cycles, due to the poor programmability, restricted software simulation, and slow code generation, respectively. Such limited productivity often defeats the purpose of HLS and hinder programmers from adopting HLS for task-parallel fpga *** this paper, we extend the HLS C++ language and present a fully automated framework with programmer-friendly interfaces, universal software simulation, and fast code generation to overcome these limitations. Experimental results based on a wide range of real-world task-parallel programs show that, on average, the lines of kernel and host code are reduced by 22% and 51%, respectively, which considerably improves the programmability. The correctness verification and the iterative QoR tuning cycles are both greatly accelerated by 3.2× and 6.8×, respectively.

关键词： high-level synthesis task-parallel program field-programmable gate array

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Network-on-Chip programmable Platform in Versal™ ACAP Architecture

Network-on-Chip Programmable Platform in Versal™ ACAP Archi...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Swarbrick, Ian Gaitonde, Dinesh Ahmad, Sagheer Gaide, Brian Arbel, Ygal Xilinx Inc San Jose CA 95124 USA

ISBN: (纸本)9781450361378

This paper outlines the Network-on-Chip (NoC) on Xilinx's next generation Versal (TM) architecture. It is a hardened NoC that is present in Xilinx's next-generation 7nm architecture devices. These devices include many other new hardened features that make up the Adaptable Computing Acceleration Platform (ACAP) devices. There is a trend in fpga devices of hardening many commonly used components such as processors, memory controllers and other IO controllers. The next generation of Xilinx devices take this a step further by providing a device-global memory mapped NoC which connects these components and the fabric in an integrated fashion. The NoC unifies communication between the processor system, fpga fabric, memory subsystem and other hardened accelerator functions. This paper gives an overview of the Versal architecture NoC. It also motivates some of the specific characteristics of the architecture. We show how hardening the NoC lets users quickly implement high performance system level interconnect.

关键词： ACAP Versal fpga Stacked Silicon SSIT Adaptable Compute Acceleration Platform NoC fpga Architecture fpga CAD Xilinx

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Classifying Computations on Multi-Tenant fpgas 21

Classifying Computations on Multi-Tenant FPGAs

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The 2021 acm/sigda international symposium on field-programmable gate arrays

作者： Mustafa Gobulukoglu Colin Drewes Bill Hunter Dustin Richmond Ryan Kastner University of California San Diego San Diego CA USA Georgia Tech Research Institute Atlanta GA USA University of Washington Seattle WA USA

ISBN: (纸本)9781450382182

Modern data centers leverage large fpgas to provide low latency, high throughput, and low energy computation. fpga multi-tenancy is an attractive option to maximize utilization, yet it opens the door to unique security threats. In this work, we develop a remote classification pipeline that targets the confidentiality of multi-tenant cloud fpga environments. We design a unique Dual-Edged voltage fluctuation sensor that measures subtle changes in the power distribution network caused by co-located computations. The sensor measurements are given to a classification pipeline that is able to deduce information about co-located applications including the type of computation and its implementation. We study the importance of the trace length, signal conditioning algorithms, and other aspects that affect classification accuracy. Our results show that we can determine if another co-tenant is present with 96% accuracy. We can classify with 98% accuracy whether a power waster circuit is operating. Furthermore, we are able to determine if a cryptographic operation is occurring, differentiate between different cryptographic algorithms (AES and PRESENT) and microarchitectural implementations (Microblaze, ORCA, and PicoRV32).

关键词： programmable logic sensor hardware security power distribution network side-channel analysis neural network multi-tenant fpga

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