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检索条件"任意字段=2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013"

共 809 条记录，以下是711-720 订阅

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Interconnect pipelining in a throughput-intensive fpga architecture 01

Interconnect pipelining in a throughput-intensive FPGA archi...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (fpga 2001)

作者： Singh, A. Mukherjee, A. Marek-Sadowska, M. Department of Electrical Engineering University of California Santa Barbara CA 93106 United States

ISBN: (纸本)9781581133417

Wave-steering is a new design methodology that realizes high throughput circuits by embedding layout friendly synthesized structures in silicon. In the wave-steering design methodology, circuits inherently utilize latches. Inside the synthesized structures they are used for signal skewing, and on the interconnects to guarantee the correct arrival times at the inputs. Recently, we proposed a novel high-throughput fpga architecture based on the wavesteering design principle to handle throughput-intensive applications. Previously our work was focussed mainly on the Logic Block (LB) design. In this paper we discuss a pipelined interconnect scheme to support the strict timing requirements that is necessitated by the wave-steered design style. We characterize designs that best fit the new architecture and show that as technology scales down towards deep submicron (DSM), this fpga fabric shows an increasing throughput performance.

关键词： field programmable gate arrays

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Simultaneous logic decomposition with technology mapping in fpga designs 01

Simultaneous logic decomposition with technology mapping in ...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (fpga 2001)

作者： Chen, G. Cong, J. Computer Science Department University of California Los Angeles CA 90095 United States

ISBN: (纸本)9781581133417

Conventional technology mapping algorithms for SRAM-based field programmable gate arrays (fpgas) are normally carried out on a fixed logic decomposition of a circuit. The impact of logic decomposition on delay and area of the technology mapping solutions is not well understood. In this paper, we present an algorithm named SLDMap that performs delay-minimized technology mapping on a large set of decompositions and simultaneously controls the mapping area under delay constraints. Our study leads to two conclusions: (1) For depth minimization, the best algorithms in conventional flow (dmig + CutMap) produce satisfactory results with a short runtime, even with a fixed decomposition;(2) When all the structural decompositions of the 6-bounded Boolean network are explored, SLDMap consistently outperforms the state-of-the-art separate flow (dmig + CutMap) by 12% in depth and 10% in area on average;it also consistently outperforms the state-of-the-art combined approach dogma by 8% in depth and 6% in area on average.

关键词： field programmable gate arrays

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A memory coherence technique for online transient error recovery of fpga configurations 01

A memory coherence technique for online transient error reco...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (fpga 2001)

作者： Huang, W.-J. McCluskey, E.J. Center for Reliable Computing Department of Electrical Engineering Stanford University Stanford CA 94305-4055 United States

ISBN: (纸本)9781581133417

The partial reconfiguration feature of some of the current-generation field programmable gate arrays (fpgas) can improve dependability by detecting and correcting errors in on-chip configuration data. Such an error recovery process can be executed online with minimal interference of user applications. However, because Look-up Tables (LUTs) in Configurable Logic Blocks (CLBs) of fpgas can also implement memory modules for user applications, a memory coherence issue arises such that memory contents in user applications may be altered by the online configuration data recovery process. In this paper, we investigate this memory coherence problem and propose a memory coherence technique that does not impose extra constraints on the placement of memory-configured LUTs. Theoretical analyses and simulation results show that the proposed technique guarantees the memory coherence with a very small (on the order of 0.1%) execution time overhead in user applications.

关键词： field programmable gate arrays

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An fpga-based video compressor for H.263 compatible bit streams 01

An FPGA-based video compressor for H.263 compatible bit stre...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (fpga 2001)

作者： Lienhart, G. Männer, R. Lay, R. Noffz, K.H. Dept. for Computer Science V University of Mannheim D-68131 Mannheim Germany

ISBN: (纸本)9781581133417

This paper presents an fpga architecture for video encoding according to the H.263 standard for video teleconferencing systems. The implementation is based on an off-the-shelf fpga and is embedded in a PCI plug-in card with on-board SRAM plus external SRAM. The most complex part of the H.263 protocol, a base-line encoder, was implemented. The strategies, which have been applied to build the complex encoding operations, are treated in this paper. The complete application is able to operate at 30 MHz. This leads to a maximum compression speed of 120 Mbit/s allowing simultaneous real-time operation of several video streams in a single reconfigurable chip. Enhanced coding options can also become implemented with present-day fpgas. The use of fpga technology enables the adaptation of hardware to various protocols and environments by software and therefore saves development time and hardware costs.

关键词： field programmable gate arrays

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Configuration compression for fpga-based embedded systems 01

Configuration compression for FPGA-based embedded systems

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (fpga 2001)

作者： Dandalis, A. Prasanna, V.K. Electrical Engineering - Systems University of Southern California 3740 McClintock Avenue Los Angeles CA 90089-2562 United States

ISBN: (纸本)9781581133417

fpgas are a promising technology for developing high-performance embedded systems. The density and performance of fpgas have drastically improved over the past few years. Consequently, the size of the configuration bit-streams has also increased considerably. As a result, the cost-effectiveness of fpga-based embedded systems is significantly affected by the memory required for storing various fpga configurations. This paper proposes a novel compression technique that reduces the memory required for storing fpga configurations and results in high decompression efficiency. Decompression efficiency corresponds to the decompression hardware cost as well as the decompression rate. The proposed technique is applicable to any SRAM-based fpga device since configuration bit-streams are processed as raw data. The required decompression hardware is simple and is independent of the individual semantics of configuration bit-streams or specifc features of the on-chip configuration mechanism. Moreover, the time to configure the device is not affected by our compression technique. Using our technique, we demonstrate up to 41% savings in memory for configuration bit-streams of several real-world applications.

关键词： field programmable gate arrays

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LRoute: A delay minimal router for hierarchical CPLDs 01

LRoute: A delay minimal router for hierarchical CPLDs

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (fpga 2001)

作者： Lee, K.K. Wong, M.D.F. Synopsys Inc. 700 E. Middlefield Rd Mountain View CA 94043 United States

ISBN: (纸本)9781581133417

This paper describes LRoute, a novel router for the popular and scalable hierarchical Complex programmable Logic Devoices (CPLDs). CPLD routing has constraints om routing topologies due to architectural limitations and performance considerations. These constraints make the problem quite different from fpga routing and render the routing problem more complicated. Extensions of popular fpga routers like the maze router performs poorly on such CPLDs. There is also little published work on CPLD routing. LRoute uses a different paradigm based on the Lagrangian Relaxation framework in the theory of mathematical programming. It respects the topology constraints imposed and routes a circuit with minimum delay. We tested this router on a set of industry problems that commercial software failed to route. Our router was able to route all of them very quickly.

关键词： programmable logic controllers

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Matching and searching analysis for parallel hardware implementation on fpgas 01

Matching and searching analysis for parallel hardware implem...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (fpga 2001)

作者： Moisset, P. Diniz, P. Park, J. University of Southern California Information Sciences Institute 4676 Admiralty Way Marina del Rey CA 90292 United States

ISBN: (纸本)9781581133417

Matching and searching computations play an important role in the indexing of data. These computations are typically encoded in very tight loops with a single index variable and a simple search/matching predicate. Their inherent sequential nature, either because of data dependences but more often because of very strong control dependences, makes it impossible to apply existing data dependence and parallelization analysis to exploit significant levels parallelism on traditional architectures. This paper describes a class of searching and matching computations and describes a mapping strategy to map these computations to hardware. We have developed a compiler analysis in SUIF using array data dependence analysis and implicit loop unrolling analysis to expose more parallelism for the parallel evaluation of these computations. Our compiler generates parallel hardware specifications in VHDL. The resulting parallel hardware yields significant performance improvements when these kernel operators are repeated over shifted portions of the input data on fpga-based computing architectures.

关键词： field programmable gate arrays

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Reprogrammable network packet processing on the field programmable Port Extender (FPX) 01

Reprogrammable network packet processing on the Field Progra...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (fpga 2001)

作者： Lockwood, J.W. Naufel, N. Turner, J.S. Taylor, D.E. Department of Computer Science Applied Research Lab. Washington University 1 Brookings Drive Saint Louis MO 63130 United States

ISBN: (纸本)9781581133417

A prototype platform has been developed that allows processing of packets at the edge of a multi-gigabit-per-second network switch. This system, the field programmable Port Extender (FPX), enables packet processing functions to be implemented as modular components in reprogrammable hardware. All logic on the on the FPX is implemented in two field programmable gate arrays (fpgas). Packet processing functions in the system are implemented as dynamically-loadable modules. Core functionality of the FPX is implemented on an fpga called the Networking Interface Device (NID). The NID contains the logic to transmit and receive packets over a network, dynamically reprogram hardware modules, and route individual traffic flows. A full, non-blocking, switch is implemented on the NID to route packets between the networking interfaces and the modular components. Modular components of the FPX are implemented on a second fpga called the Reprogrammable Application Device (RAD). Modules are loaded onto the RAD via reconfiguration and/or partial partial reconfiguration of the fpga. Through the combination of the NID and the RAD, the FPX can individually reconfigure the packet processing functionality for one set of traffic flows, while the rest of the system continues to operate. The platform simplifies the development and deployment of new hardware-accelerated packet processing circuits. The modular nature of the system allows an active router to migrate functionality from softare plugins to hardware modules.

关键词： Packet networks

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The case for registered routing switches in field programmable gate arrays 01

The case for registered routing switches in field programmab...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (fpga 2001)

作者： Singh, D.P. Brown, S.D. Department of Electrical Engineering University of Toronto Toronto Ont. Canada

ISBN: (纸本)9781581133417

fpgas are characterized by a programmable interconnect that contains highly resistive and capacitive elements. While the configurable structure of the interconnect allows for the implementation of arbitrary circuits, it has also become a significant bottleneck for high-speed circuits. Even if there are only a few signal paths that run along long stretches of interconnect, it is these paths that may determine the maximum operating frequency of the circuit. In this paper we investigate architectural features that could allow us to automatically pipeline the delay associated with long routes without an excessive area penalty. The goal is to reschedule circuit operations in such a way that a signal may use multiple clock cycles to traverse a long route, rather than requiring a single long clock period. This rescheduling would not effect the timing of the visible outputs (no latency is added to the overall system). Specifically, we analyze the effects of adding a small number of registered routing switches to an fpga architecture with segmented routing resources. A parameterized fpga architecture is studied where the percentage of registered routing switches is varied and the speed improvement and area penalty is evaluated. Novel algorithms are presented that allow a circuit to best utilize an architecture with a given percentage of registered switches. We believe that this is the first study that attempts to evauate the tradeoffs associated with switches required in fpga architectures. Our experiments indicate that the architectural features introduced can produce significant speedup for high speed circuits without excessive area costs. We believe that these techniques will become increasingly important in the future as deep sub-micron process technologies shrink, and wire delays become even more significant.

关键词： field programmable gate arrays

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Runtime and quality tradeoffs in fpga placement and routing 01

Runtime and quality tradeoffs in FPGA placement and routing

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (fpga 2001)

作者： Mulpuri, C. Hauck, S. Department of Electrical Engineering University of Washington Seattle WA 98195 United States

ISBN: (纸本)9781581133417

Many applications of fpgas, especially logic emulation and custom computing, require the quick placement and routing of circuit designs. In these applications, the advantages fpga-based systems have over software simulation are diminished by the long run-times of current CAD software used to map the circuit onto fpgas. To improve the run-time advantage of fpga systems, users may be willing to trade some mapping quality for a reduction in CAD tool runtimes. In this paper, we seek to establish how much quality degradation is necessary to achieve a given runtime improvement. For this purpose, we implemented and investigated numerous placement and routing algorithms for fpgas. We also developed new tradeoff-oriented algorithms, where a tuning parameter can be used to control this quality vs. runtime tradeoff. We show how different algorithms can achieve different points within this tradeoff spectrum, as well as how a single algorithm can be tuned to form a curve in the spectrum. We demonstrate that the algorithms vary widely in their tradeoffs, with the fastest algorithm being 8x faster than the slowest, and the highest quality algorithm being 5x better than the least quality algorithm. Compared to the commercial Xilinx CAD tools, we can achieve a 3x speed-up by allowing 1.27x degradation in quality, and a factor of 1.6x quality improvement with 2x slowdown.

关键词： field programmable gate arrays

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