检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

779 篇 会议
30 篇 期刊文献

馆藏范围

809 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

635 篇 工学
- 529 篇 计算机科学与技术...
- 314 篇 软件工程
- 250 篇 电子科学与技术（可...
- 201 篇 电气工程
- 88 篇 信息与通信工程
- 52 篇 控制科学与工程
- 32 篇 动力工程及工程热...
- 31 篇 机械工程
- 24 篇 仪器科学与技术
- 16 篇 生物工程
- 11 篇 冶金工程
- 10 篇 建筑学
- 10 篇 土木工程
- 10 篇 化学工程与技术
- 9 篇 光学工程
- 8 篇 材料科学与工程（可...
- 8 篇 生物医学工程（可授...
- 3 篇 农业工程
228 篇 理学
- 172 篇 数学
- 47 篇 物理学
- 20 篇 统计学（可授理学、...
- 17 篇 生物学
- 10 篇 系统科学
- 8 篇 化学
55 篇 管理学
- 47 篇 管理科学与工程(可...
- 30 篇 工商管理
- 9 篇 图书情报与档案管...
14 篇 经济学
- 14 篇 应用经济学
14 篇 医学
- 13 篇 特种医学
11 篇 法学
- 9 篇 社会学
3 篇 农学
2 篇 教育学
1 篇 文学

主题

433 篇 field programmab...
232 篇 field programmab...
46 篇 hardware
32 篇 fpga
30 篇 clocks
28 篇 computer archite...
21 篇 table lookup
21 篇 delays
17 篇 random access me...
16 篇 routing
16 篇 software
15 篇 switches
12 篇 digital signal p...
11 篇 throughput
11 篇 system-on-chip
11 篇 algorithm design...
10 篇 multiplexing
10 篇 logic gates
10 篇 bandwidth
10 篇 educational inst...

机构

6 篇 univ of toronto ...
5 篇 school of comput...
5 篇 university of to...
5 篇 univ of toronto
5 篇 univ of californ...
5 篇 altera corporati...
4 篇 univ british col...
4 篇 nanyang technol ...
4 篇 dept. of cs 256-...
4 篇 department of el...
4 篇 state key lab of...
4 篇 intel corporatio...
3 篇 computer science...
3 篇 department of ee...
3 篇 department of el...
3 篇 department of el...
3 篇 xilinx inc. san ...
3 篇 technical univer...
3 篇 northwestern uni...
3 篇 nanyang technolo...

作者

20 篇 cong jason
19 篇 rose jonathan
11 篇 betz vaughn
10 篇 wawrzynek john
9 篇 dehon andré
9 篇 hauck scott
9 篇 zhang zhiru
8 篇 chen deming
7 篇 wilton steven j....
7 篇 schmit herman
7 篇 constantinides g...
7 篇 chow paul
7 篇 langhammer marti...
6 篇 cheung peter y. ...
6 篇 wilton steven j....
6 篇 pasca bogdan
6 篇 li fei
6 篇 prasanna viktor ...
5 篇 jason cong
5 篇 fahmy suhaib a.

语言

798 篇 英文
6 篇 其他
4 篇 中文
1 篇 西班牙文

检索条件"任意字段=2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013"

共 809 条记录，以下是71-80 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Versal: The Xilinx Adaptive Compute Acceleration Platform (ACAP) 19

Versal: The Xilinx Adaptive Compute Acceleration Platform (A...

引用

acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Vissers, Kees Xilinx 2100 All Programmable Dr San Jose CA 95124 USA

ISBN: (纸本)9781450361378

In this presentation I will present the new Adaptive Compute Acceleration Platform. I will show the overall system architecture of the family of devices including the Arm cores (scalar engines), the programmable logic (Adaptable Engines) and the new vector processor cores (AI engines). I will focus on the new AI engines in more detail and show the architecture, the integration in the total device, the programming environment and some applications, including Machine Learning and 5G wireless applications.

关键词： Versal AI engine VLIW processor

来源：评论

学校读者我要写书评

暂无评论

The P4→Netfpga Workflow for Line-Rate Packet Processing 19

The P4→NetFPGA Workflow for Line-Rate Packet Processing

引用

acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Ibanez, Stephen Brebner, Gordon McKeown, Nick Zilberman, Noa Stanford Univ Stanford CA 94305 USA Xilinx Labs San Jose CA USA Univ Cambridge Cambridge England

ISBN: (纸本)9781450361378

P4 has emerged as the de facto standard language for describing how network packets should be processed, and is becoming widely used by network owners, systems developers, researchers and in the classroom. The goal of the work presented here is to make it easier for engineers, researchers and students to learn how to program using P4, and to build prototypes running on real hardware. Our target is the Netfpga SUME platform, a 4 x 10 Gb/s PCIe card designed for use in universities for teaching and research. Until now, Netfpga users have needed to learn an HDL such as Verilog or VHDL, making it off limits to many software developers and students. Therefore, we developed the P4 -> Netfpga workflow, allowing developers to describe how packets are to be processed in the high-level P4 language, then compile their P4 programs to run at line rate on the Netfpga SUME board. The P4 -> Netfpga workflow is built upon the Xilinx P4-SDNet compiler and the Netfpga SUME open source code base. In this paper, we provide an overview of the P4 programming language and describe the P4 -> Netfpga workflow. We also describe how the workflow is being used by the P4 community to build research prototypes, and to teach how network systems are built by providing students with hands-on experience working with real hardware.

关键词： programmable data-planes fpga p4

来源：评论

学校读者我要写书评

暂无评论

fpga-based Acceleration of Binary Neural Network Training with Minimized Off-Chip Memory Access

FPGA-based Acceleration of Binary Neural Network Training wi...

引用

IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Chundi, Pavan Kumar Liu, Peiye Park, Sangsu Lee, Seho Seok, Mingoo Columbia Univ Dept Elect Engn New York NY 10027 USA SK Hynix Semicond Future Memory Res San Jose CA USA

ISBN: (纸本)9781728129549

In this paper, we examine the feasibility of fpga as a platform for training a convolutional binary-weight neural network. Training a neural network requires more data movement compared to inference. Acceleration of training on an fpga is, therefore, a challenge because the data movement increases off-chip memory accesses. We try to address this problem by storing most of the data in the on-chip memory and adopting batch renormalization. This allows for training a large network by reducing the required intermediate data and its movement. For the case where all data except the input images can be stored on an fpga chip, we present an accelerator for training CNNs to classify the CIFAR-10 dataset. Further, we study the impact of network size on performance and energy of fpga and GPU. Our accelerator mapped in the Arria 10 fpga chip obtains up-to 9.33X higher energy efficiency compared to the Nvidia Geforce GTX 1080 Ti GPU at similar performance.

关键词： Training Neural networks field programmable gate arrays Backpropagation Convolutional codes Acceleration Convolution

来源：评论

学校读者我要写书评

暂无评论

Unleashing the Power of fpgas as programmable Switches 20

Unleashing the Power of FPGAs as Programmable Switches

引用

Proceedings of the 2020 acm/sigda international symposium on field-programmable gate arrays

作者： Thomas Luinaud Thibaut Stimpfling Jeferson Santiago Da Silva Yvon Savaria J.M. Pierre Langlois Polytechnique Montréal Montréal PQ Canada Polytechnique Montréal Montreal PQ Canada Polytechnique Montréal Montréal Canada

ISBN: (纸本)9781450370998

The P4 language and the PISA architecture have revolutionized the field of networking. Thanks to P4 and PISA, new networking applications and protocols can be rapidly evaluated on high performance switches. While P4 allows the expression of a wide range of packet processing algorithms, current programmable switch architecture limit the overall processing flexibility. To address this shortcoming recent work have proposed to implement PISA on fpgas. However, little effort has been devoted to analyze whether fpgas are good candidates to implement PISA. In this work, we take a step back and evaluate the micro-architecture efficiency of various PISA blocks. Using a theoretical analysis and experiments, we demonstrate that current fpga architecture drastically limit the performance of a few PISA blocks. Thus, we explore two avenues to alleviate these shortcomings. First, we identify some network applications that are well tailored to current fpgas. Second, to support a wider range of networking applications, we propose modifications to the fpga architecture which can also be of interest outside the networking field.

关键词： data plane network p4

来源：评论

学校读者我要写书评

暂无评论

fpga 2015 - 2015 acm/sigda international symposium on field-programmable gate arrays

FPGA 2015 - 2015 ACM/SIGDA International Symposium on Field-...

引用

acm/sigda international symposium on field-programmable gate arrays, fpga 2015

ISBN: (纸本)9781450333153

The proceedings contain 35 papers. The topics discussed include: using source-level transformations to improve high-level synthesis debug and validation on fpgas;high-level design tools for floating point fpgas;software-driven hardware development;InTime: a machine learning approach for efficient selection of fpga CAD tool parameters;enhancing hardware design flows with MyHDL;rapid prototyping of wireless physical layer modules using flexible software/hardware design flow;application of specific delay window routing for timing optimization in fpga designs;application of specific delay window routing for timing optimization in fpga designs;fine-grained interconnect synthesis;delay-bounded routing for shadow registers;EURECA: on-chip configuration generation for effective dynamic data access;energy-efficient discrete signal processing with field programmable analog arrays (FPAAs);expanding OpenFlow capabilities with virtualized reconfigurable hardware.

关键词：

来源：评论

学校读者我要写书评

暂无评论

High-Performance QR Decomposition for fpgas 18

High-Performance QR Decomposition for FPGAs

引用

acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Langhammer, Martin Pasca, Bogdan Intel Programmable Solut Grp Swindon Wilts England Intel Programmable Solut Grp Paris France

ISBN: (纸本)9781450356145

QR decomposition (QRD) is of increasing importance for many current applications, such as wireless and radar. Data dependencies in known algorithms and approaches, combined with the data access patterns used in many of these methods, restrict the achievable performance in software programmable targets. Some fpga architectures now incorporate hard floating-point (HFP) resources, and in combination with distributed memories, as well as the flexibility of internal connectivity, can support high-performance matrix arithmetic. In this work, we present the mapping to parallel structures with inter-vector connectivity of a new QRD algorithm. Based on a Modified Gram-Schmidt (MGS) algorithm, this new algorithm has a different loop organization, but the dependent functional sequences are unchanged, so error analysis and numerical stability are unaffected. This work has a theoretical sustained-to-peak performance close to 100% for large matrices, which is roughly three times the functional density of the previously best known implementations. Mapped to an Intel Arria 10 device, we achieve 80us for a 256x256 single precision real matrix, for a 417 GFLOP equivalent. This corresponds to a 95% sustained to peak ratio, for the portion of the device used for this work.

关键词： QRD MGS fpga Arria10 throughput

来源：评论

学校读者我要写书评

暂无评论

P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in fpgas 18

P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s S...

引用

acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： da Silva, Jeferson Santiago Boyer, Francois-Raymond Langlois, J. M. Pierre Polytech Montreal Montreal PQ Canada

ISBN: (纸本)9781450356145

Packet parsing is a key step in SDN-aware devices. Packet parsers in SDN networks need to be both reconfigurable and fast, to support the evolving network protocols and the increasing multi-gigabit data rates. The combination of packet processing languages with fpgas seems to be the perfect match for these requirements. In this work, we develop an open-source fpga-based configurable architecture for arbitrary packet parsing to be used in SDN networks. We generate low latency and high-speed streaming packet parsers directly from a packet processing program. Our architecture is pipelined and entirely modeled using templated C++ classes. The pipeline layout is derived from a parser graph that corresponds to a P4 code after a series of graph transformation rounds. The RTL code is generated from the C++ description using Xilinx Vivado HLS and synthesized with Xilinx Vivado. Our architecture achieves a 100 Gb/s data rate in a Xilinx Virtex-7 fpga while reducing the latency by 45% and the LUT usage by 40% compared to the state-of-the-art.

关键词： fpga packet parsers HLS programmable networks P4

来源：评论

学校读者我要写书评

暂无评论

Architecture Exploration for HLS-Oriented fpga Debug Overlays 18

Architecture Exploration for HLS-Oriented FPGA Debug Overlay...

引用

acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Jamal, Al-Shahna Goeders, Jeffrey Wilton, Steven J. E. Univ British Columbia Vancouver BC Canada Brigham Young Univ Provo UT 84602 USA

ISBN: (纸本)9781450356145

High-Level Synthesis (HLS) promises improved designer productivity, but requires a debug ecosystem that allows designers to debug in the context of the original source code. Recent work has presented in-system debug frameworks where instrumentation added to the design collects trace data as the circuit runs, and a software tool that allows the user to replay the execution using the captured data. When searching for the root cause of a bug, the designer may need to modify the instrumentation to collect data from a new part of the design, requiring a lengthy recompile. In this paper, we propose a flexible debug overlay family that provides software-like debug turn-around times for HLS generated circuits. At compile time, the overlay is added to the design and compiled. At debug time, the overlay can be configured many times to implement specific debug scenarios without a recompilation. This paper first outlines a number of "capabilities" that such an overlay should have, and then describes architectural support for each of these capabilities. The cheapest overlay variant allows selective variable tracing with only a 1.7% increase in area overhead from the baseline debug instrumentation, while the deluxe variant offers 2x-7x improvement in trace buffer memory utilization with conditional buffer freeze support.

关键词： field-programmable gate Array Debugging High-Level Synthesis

来源：评论

学校读者我要写书评

暂无评论

Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software programmable fpgas 18

Rosetta: A Realistic High-Level Synthesis Benchmark Suite fo...

引用

acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Zhou, Yuan Gupta, Udit Dai, Steve Zhao, Ritchie Srivastava, Nitish Jin, Hanchen Featherston, Joseph Lai, Yi-Hsiang Liu, Gai Velasquez, Gustavo Angarita Wang, Wenping Zhang, Zhiru Cornell Univ Sch Elect & Comp Engn Ithaca NY 14853 USA Harvard Univ Comp Sci Cambridge MA 02138 USA Univ Nacl Colombia Syst Engn & Comp Sci Bogota Colombia Zhejiang Univ Elect & Informat Engn Hangzhou Peoples R China

ISBN: (纸本)9781450356145

Modern high-level synthesis (HLS) tools greatly reduce the turnaround time of designing and implementing complex fpga-based accelerators. They also expose various optimization opportunities, which cannot be easily explored at the register-transfer level. With the increasing adoption of the HLS design methodology and continued advances of synthesis optimization, there is a growing need for realistic benchmarks to (1) facilitate comparisons between tools, (2) evaluate and stress-test new synthesis techniques, and (3) establish meaningful performance baselines to track progress of the HLS technology. While several HLS benchmark suites already exist, they are primarily comprised of small textbook-style function kernels, instead of complete and complex applications. To address this limitation, we introduce Rosetta, a realistic benchmark suite for software programmable fpgas. Designs in Rosetta are fully-developed applications. They are associated with realistic performance constraints, and optimized with advanced features of modern HLS tools. We believe that Rosetta is not only useful for the HLS research community, but can also serve as a set of design tutorials for non-expert HLS users. In this paper we describe the characteristics of our benchmarks and the optimization techniques applied to them. We further report experimental results on an embedded fpga device as well as a cloud fpga platform.

关键词： high-level synthesis fpga heterogeneous computing reconfigurable computing benchmarking

来源：评论

学校读者我要写书评

暂无评论

Towards Trainable Synthesis for Optimized Circuit Deployment on fpga 29

Towards Trainable Synthesis for Optimized Circuit Deployment...

引用

29th international symposium on Rapid System Prototyping, RSP 2018

作者： Legault, Jean-Philippe Patros, Panagiotis Kent, Kenneth B. Faculty of Computer Science University of New Brunswick FrederictonNB Canada Department of Computer Science University of Waikato Hamilton Waikato New Zealand

ISBN: (纸本)9781538675571

field programmable gate arrays (fpgas) utilize multiple programmable elements and non-programmable blocks. After synthesizing an input Hardware Design Language (HDL) design into a circuit, optimizations are used to discover a satisfactory deployment on a target fpga. HDLs' compound operations, such as addition, can be implemented in various ways and thus, multiple but functionally equivalent circuits can be synthesized. To leverage this, we propose a methodology that first enables configurable synthesis of compound operations. Second, it trains the system using a set of HDL files and architectures to optimize target performance objectives, such as critical path length and power. We prototyped our technique in the open source Verilog-To-Routing (VTR) tool. We subsequently produced two configuration files targeting different deployment objectives;experimental results with the VTR Verilog benchmarks revealed significant improvements. © 2018 IEEE.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共81页 << < 4 5 6 7 8 9 10 11 12 13 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：