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检索条件"任意字段=2014 8th Conference on Design and Architectures for Signal and Image Processing, DASIP 2014"

共 24 条记录，以下是1-10 订阅

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architectures and Key Technical Challenges for Space-Terrestrial Heterogeneous Networks 8th

Architectures and Key Technical Challenges for Space-Terrest...

引用

8th International conference on Communications, signal processing, and Systems, CSPS 2019

作者： Zhang, Yang Mu, Chao Lu, Zhou Xu, Fangmin Xiao, Ye China Academic Electronic and Information Technology Beijing100041 China School of Information and Communication Engineering Beijing University of Post and Telecommunications Beijing100876 China

ISBN: (纸本)9789811394089

Possessing the capability of breaking through the limitation of geographic conditions, Space-Terrestrial Heterogeneous networks play a significant role for global coverage capacity, which however pose new challenges to the network architecture design. In this paper, we first propose novel architectures for the considered space-terrestrial heterogeneous networks. On this basis, some key technical issues in the developed architectures are comprehensively discussed, including protocol design, Integrated Routing and so on, which pave the way for extensive applications of the Space-Terrestrial Heterogeneous networks. © 2020, Springer Nature Singapore Pte Ltd.

关键词： Network architecture

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Visual attention model with a novel learning strategy and its application to target detection from SAR images 1

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8th International conference on Brain Inspired Cognitive Systems, BICS 2016

作者： Gao, Fei Xue, Xiangshang Wang, Jun Sun, Jinping Hussain, Amir Yang, Erfu School of Electronic and Information Engineering Beihang University Beijing100191 China Cognitive Signal-Image and Control Processing Research Laboratory School of Natural Sciences University of Stirling StirlingFK9 4LA United Kingdom Space Mechatronic Systems Technology Laboratory Department of Design Manufacture and Engineering Management University of Strathclyde GlasgowG1 1XJ United Kingdom

ISBN: (数字)9783319496856

ISBN: (纸本)9783319496849

the selective visual attention mechanism in human visual system helps human to act efficiently when dealing with massive visual information. Over the last two decades, biologically inspired attention model has drawn lots of research attention and many models have been proposed. However, the top-down cues in human brain are still not fully understood, which makes top-down models not biologically plausible. this paper proposes an attention model containing both the bottom-up stage and top-down stage for the target detection from SAR (Synthetic Aperture Radar) images. the bottom-up stage is based on the biologically-inspired Itti model and is modified by taking fully into account the characteristic of SAR images. the top-down stage contains a novel learning strategy to make the full use of prior information. It is an extension of the bottom-up process and more biologically plausible. the experiments in this research aim to detect vehicles in different scenes to validate the proposed model by comparing with the well-known CFAR (constant false alarm rate) algorithm. © Springer International Publishing AG 2016.

关键词： Object detection

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A Review of World's Fastest Connected Component Labeling Algorithms: Speed and Energy Estimation 8

A Review of World's Fastest Connected Component Labeling Alg...

引用

8th conference on design and architectures for signal and image processing (dasip)

作者： Cabaret, Laurent Lacassagne, Lionel Oudni, Louiza Univ Paris Sud Lab Rech Informat F-91405 Orsay France

ISBN: (纸本)9791092279061

Optimizing connected component labeling is currently a very active research field. the current most effective algorithms although close in their design are based on different memory/computation trade-offs. this paper presents a review of these algorithms and a detailed benchmark on several Intel and ARM embedded processors that allows to focus on their advantages and drawbacks and to highlight how processor architecture impact them.

关键词： connected component algorithms Processor architectures

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Video++, a modern image and video processing C++ framework 8

Video++, a modern image and video processing C++ framework

引用

2014 8th conference on design and architectures for signal and image processing, dasip 2014

作者： Garrigues, Matthieu Manzanera, Antoine ENSTA-ParisTech 828 Boulevard des Maréchaux Palaiseau Cedex91762 France

ISBN: (纸本)9791092279054

We present in this paper Video++, a new framework targeting image and video applications running on multi-core processors. While offering a high expressive power, we show that it generates code running up to 32 times faster than the naive equivalents. Taking advantage of the new C++11/C++14 features, tools, we propose simple abstractions matching the performance of hand optimized code. this paper gives an overview of the library and demonstrates its efficiency with some benchmarks. © 2014 European Electronic Chips & Systems design Initiative - ECSI.

关键词： Video signal processing

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Hardware Architecture design and Implementation for FMCW Radar signal processing Algorithm 8

Hardware Architecture Design and Implementation for FMCW Rad...

引用

8th conference on design and architectures for signal and image processing (dasip)

作者： Eugin, Hyun Lee, Jonghun DGIST ART Adv Radar Technol Lab Robot Res Div Daegu South Korea

ISBN: (纸本)9791092279061

Chirp-sequence-based Frequency Modulation Continuous Wave (FMCW) radar is effective at detecting range and velocity of a target. However, the target detection algorithm is based on two-dimensional Fast Fourier Transform, which uses a great deal of data over several PRIs (Pulse Repetition Intervals). In particular, if the multiple-receive channel is employed to estimate the angle position of a target;even more computational complexity is required. In this paper, we report on how a newly developed signal processing module is implemented in the FPGA, and on its performance measured under test conditions. Moreover, we have presented results from analysis of the use of hardware resources and processing times.

关键词： FMCW radar detection algorithm chirp sequence

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A Vision Location System design of Glue Dispensing Robot 8th

A Vision Location System Design of Glue Dispensing Robot

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8th International conference on Intelligent Robotics and Applications (ICIRA)

作者： Wang, Nianfeng Liu, Jinghui Wei, Shuai Zhang, Xianmin S China Univ Technol Sch Mech & Automobile Engn Guangzhou 510641 Guangdong Peoples R China

ISBN: (纸本)9783319228730;9783319228723

the location accuracy of the workpiece is the key problem in the glue dispensing operation of the automobile engine cover. A vision location system is designed for the glue dispensing robot to locate the position of the feature points in the engine cover. the system correct the original teaching trajectory in real time to maintain the accuracy of the gluing operation. the system is based on a digital signal processor (DSP) dedicated to image processing for its real-time performance. image preprocessing operations including gray value linear transformation and median filtering are applied to modify the image quality for the subsequent feature-point detection procedure. Experiments are conducted and the result shows that the system is feasible after the calibration of the camera.

关键词： Vision location Robot gluing DSP Feature point detection

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PHAT: A TECHNOLOGY FOR PROTOTYPING PARALLEL HETEROGENEOUS architectures 8

PHAT: A TECHNOLOGY FOR PROTOTYPING PARALLEL HETEROGENEOUS AR...

引用

8th conference on design and architectures for signal and image processing (dasip)

作者： Wink, thorsten Koch, Andreas Tech Univ Darmstadt Embedded Syst & Applicat Grp Darmstadt Germany

ISBN: (纸本)9791092279061

this paper presents the Parallel Heterogeneous Architecture Technology (PHAT), a scalable design methodology for prototyping and evaluating heterogeneous arrays of software-programmable VLIW processors and both manually designed and automatically-compiled custom hardware accelerators, using a shared memory architecture for communication. We discuss the trade-offs and break-even point for switching from bus-based to network-on-chip interconnects, the interface and protocols for connecting distributed on-chip caches and multi-bank out-of-order offchip- memories, as well as the impact of floorplanning on the quality of results for implementation on Xilinx Virtex 6 LX 760 devices. the capabilities are evaluated at the system-level on the multi-FPGA Convey HC-1ex hybrid-core computer, accessing its high-performance memory system, and integrating r-VEX processor cores with IP blocks for SHA and FFT computations.

关键词： on-chip cache shared memory systems PROTOTYPE circuit layout Secure Hashing Algorithm ARCHITECTURE EIS IMPLEMENTATION PLANS PROCESSOR protocols Parallel Lines Memory architecture system level BREAKEVEN

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Optimized fixed point implementation of a local stereo matching algorithm onto C66x DSP 8

Optimized fixed point implementation of a local stereo match...

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8th conference on design and architectures for signal and image processing (dasip)

作者： Menant, Judicael Pressigout, Muriel Morin, Luce Nezan, Jean-Francois Univ Europeenne Bretagne CNRS INSA IETRUMR 6164 20 Ave Buttes Coesmes F-35708 Rennes France

ISBN: (纸本)9791092279061

Stereo matching techniques aim at reconstructing disparity maps from a pair of images. the use of stereo matching techniques in embedded systems is very challenging due to the complexity of the state-of-the-art algorithms. An efficient local stereo matching algorithm has been chosen from the literature and implemented on a c6678 DSP. Arithmetic simplifications such as approximation by piecewise linear functions and fixed point conversions are proposed. thanks to factorisation and precomputing, the memory footprint is reduced by a factor 13 to fit on the memory footprint available on embedded systems. A 14.5 fps speed (factor 60 speed-up) has been reached with a small quality loss on the final disparity map.

关键词： Fixed point Embedded systems Digital signal processing Desmoplakin Gene linear function mass loss N-ethylcarbaminomethyl-L-isoleucine Velocity coefficient factorization

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Demonstrating a Dataflow-based RTOS for Heterogeneous MPSoC by means of a Stereo Matching Application 8

Demonstrating a Dataflow-based RTOS for Heterogeneous MPSoC ...

引用

8th conference on design and architectures for signal and image processing (dasip)

作者： Heulot, Julien Menant, Judicael Pelcat, Maxime Nezan, Jean-Francois Morin, Luce Pressigout, Muriel Aridhi, Slaheddine UEB CNRS UMR 6164 INSA Rennes IETR 20 Ave Buttes de Coesmes Rennes France Texas Instruments France Cagnes Sur Mer France

ISBN: (纸本)9791092279061

this demonstration paper presents a multicore Real Time Operating System (RTOS) that schedules a parameterized dataflow Model of Computation (MoC) onto a multicore Digital signal Processor (DSP) at runtime. this RTOS called Synchronous Parameterized and Interfaced Dataflow Embedded Runtime (SPIDER) exploits the Parameterized and Interfaced Synchronous Dataflow (PiSDF) MoC and its features at runtime to identify locally static regions and to optimize their execution onto multicore platforms. the RTOS is used to dispatch a stereo matching algorithm tasks with a varying range of disparities. the platform used for this demonstration is a Texas Instruments Keystone II Multiprocessor System-on-Chip (MPSoC) device composed of 8 DSP cores, 4 ARM cores, a shared memory subsystem, Multicore Navigator and multiple dedicated accelerators.

关键词： Multi-core processors parameterization Runtime data flow Legal Executions Digital signal processing Desmoplakin Gene

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Closed-loop Adaptive and Stochastic Prefetch Mechanism for Data Array 8

Closed-loop Adaptive and Stochastic Prefetch Mechanism for D...

引用

8th conference on design and architectures for signal and image processing (dasip)

作者： Vincent, Lionel Mancini, Stephane Grenoble Univ PERSYVAL Lab Grenoble France Grenoble Univ TIMA Lab Grenoble France

ISBN: (纸本)9791092279061

Nowadays, one of the main limiting factor in multiprocessor development is the increasing speed gap between efficient processing elements and slow main memories. To reduce this limitation, prefetching mechanisms, implemented in memory hierarchy, attempt to predict the future data needed in local memory. However, classical proposed solutions are no longer efficient for typical access sequences in the context of image processing algorithms. In this paper, a prefetching mechanism is proposed, based on the use of the index array of access rather than memory addresses. the adaptive prediction policy takes into account both application and main memory characteristics. this mechanism enhances the Cache nD-AP, formerly statically set, to improve its performance. Experiments show that the proposed adaptive strategy is able to maintain its efficiency when the characteristics of the system dynamically change.

关键词： prefetching Self tuning image processing algorithm memory hierarchy Access Memory storage allocation adaptive prediction main memory Local Memory

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