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检索条件"任意字段=2014 9th Southern Conference on Programmable Logic, SPL 2014"

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2014 9th southern conference on programmable logic, spl 2014

2014 9th Southern Conference on Programmable Logic, SPL 2014

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2014 9th southern conference on programmable logic, spl 2014

ISBN: (纸本)9781479968480

the proceedings contain 22 papers. the topics discussed include: wavelet hardware processing unit for transient signal detection;an advanced NoC with debug services on FPGA;FPGA implementation of a binary32 floating point cube root;the Hamiltonian-based odd-even routing method for 3D networks-on-chip;proposal for parallel fixed point implementation of a radial basis function network in an FPGA;hardware-accelerated spike train generation for neuromorphic image and video processing;FPGA structures with concentrated vs distributed memory for images comparison;components for coverage-driven verification of floating-point units;hardware design of an NTT-based polynomial multiplier;PUF's performance evaluation among different Xilinx FPGAs families;design and implementation of decimal fixed-point square Root in LUT-6 FPGAs;validation of an on-chip watchdog for embedded systems exposed to radiation and conducted EMI;and synthesis of locally-clocked asynchronous systems with bundled-data implementation on FPGAs.

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FPGA implementation of a binary32 floating point cube root 9

FPGA implementation of a binary32 floating point cube root

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2014 9th southern conference on programmable logic, spl 2014

作者： Guardia, Carlos Minchola Boemo, Eduardo School of Engineering Universidad Autónoma de Madrid Madrid Spain

ISBN: (纸本)9781479968480

this paper presents the implementation of a sequential hardware core to compute a single floating point cube root compliant with the current IEEE 754-2008 standard. the design is based on Newton-Raphson recurrence, reciprocal and cube root units are implemented. Optimal performance requires two iterations for reciprocal and one for cube root units obtaining an accurate approximation of +/-3 least significant bits. Our proposal is able to be performed up to 149 Mhz over Virtex5. the hardware cost occupies 230 Slices and 12 Dsp48s taking a latency of 19 clock cycles. © 2014 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Burst-mode asynchronous controller implementation on FPG using relative timing 9

Burst-mode asynchronous controller implementation on FPG usi...

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2014 9th southern conference on programmable logic, spl 2014

作者： Manoranjan, Jotham Vaddaboina Stevens, Kenneth S. Department of Electrical and Computer Engineering University of Utah United States

ISBN: (纸本)9781479968480

A new methodology for the design of glitch free burst-mode asynchronous controllers on FPGAs is presented. the approach is based on relative timing, which enables timing driven asynchronous design. On ASICs, relative timing based asynchronous designs have achieved notable benefits in terms of power, performance and area, when compared to their synchronous counterparts. this paper adopts the relative timing based design methodology on FPGAs and presents a methodology to extract and map timing constraints to guarantee correct operation. the method presented in this paper can be used to implement a wide variety of burst-mode controllers, across various FPGAs. this will form the foundation for seamless ASIC prototyping of asynchronous designs on FPGAs as well as implementation of low power asynchronous designs on FPGAs. © 2014 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Proposal for Parallel Fixed Point Implementation of a Radial Basis Function Network in an FPGA 9

Proposal for Parallel Fixed Point Implementation of a Radial...

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9th southern conference on programmable logic (spl)

作者： de Souza, Alisson C. D. Fernandes, Marcelo A. C. Fed Univ Rio Grande Norte UFRN Dept Comp Engn & Automat DCA Natal RN Brazil

ISBN: (纸本)9781479968480

this paper proposes a parallel fixed point radial basis function (RBF) artificial neural network (ANN), implemented in a field programmable gate array (FPGA) trained with a least mean square (LMS) algorithm. the processing time and occupied area were analyzed for various fixed point formats. the problems of precision of the ANN response for nonlinear classification using the XOR gate, and interpolation using the sine function, were also analyzed in hardware implementation. the entire project was developed using the System Generator platform (Xilinx), with a Virtex-6 xc6vcx240t-1ff1156 as the target FPGA.

关键词： field programmable gate arrays interpolation least mean squares methods logic gates radial basis function networks ANN response FPGA LMS algorithm RBF Virtex-6 xc6vcx240t-1ff1156 XOR gate Xilinx artificial neural network field programmable gate array hardware implementation least mean square algorithm nonlinear classification parallel fixed point implementation processing time radial basis function network sine function system generator platform Delays Equations Field programmable gate arrays Mathematical model Neurons Table lookup Vectors Field programmable gate arrays Radial basis function networks Least mean square algorithm exclusive or gate Interpolation Least squares method Table lookup Artificial neural networks processing time logic gates Mathematical Model Fixed point

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Components for Coverage-Driven Verification of Floating-Point Units 9

Components for Coverage-Driven Verification of Floating-Poin...

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9th southern conference on programmable logic (spl)

作者： Goni, Oscar Todorovich, Elias Univ Nacl Ctr Prov Buenos Aires INTIA Inst Buenos Aires DF Argentina

ISBN: (纸本)9781479968480

this work presents the application of a mixed strategy that combines Constrained Random Tests (CRT) and Coverage Driven Verification (CDV) as well as the development of a coverage model for Floating Point Unit (FPU) designs. the proposed strategy is materialized in two key verification components for functional verification: an input generator and a verification monitor. the generator module creates random input operands based on constraints for each operation. the monitor component not only checks the result but also indicates which cases have not been tested and estimates how much of the design functionality has been tested. Tests show that using CRT-only strategy the functional does not reach the complete coverage. However, using the proposed coverage driven verification approach not only reaches 100% coverage but also speeds up the verification up to 4.5x.

关键词： floating point arithmetic formal verification system monitoring CDV CRT FPU constrained random tests coverage driven verification coverage-driven verification floating-point units functional verification input generator random input operands verification monitor Adders Field programmable gate arrays Generators Hardware Libraries Monitoring Standards Field programmable gate arrays FLOATING POINTS floating point arithmetic Verification system monitoring adders dynamos Coverage Canine distemper morbillivirus Formal verification CAthODE RAY TUBE COOLANT RETURN TANK Computer hardware Libraries

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PUF's Performance Evaluation Among Different Xilinx FPGAs Families 9

PUF's Performance Evaluation Among Different Xilinx FPGAs Fa...

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9th southern conference on programmable logic (spl)

作者： Ovilla-Martinez, Brisbane Diaz-Perez, Arturo Cinvestav Tamaulipas Informat Technol Lab Cd Victoria Tamaulipas Mexico

ISBN: (纸本)9781479968480

the FPGAs have been used as a platform to implement and validate the Physical Unclonable Function constructions. the authors validate PUFs performance using several know metrics (reliability, uniqueness, uniformity, and bit aliasing) and these test are conducted just on the FPGA used to the implementation. the problem arises when we want to use a PUF tested on a specific FPGA family into another, there is no assurance that the behavior of a PUF is the same among different families of FPGA. Up to our knowledge no previous work has been reported to evaluate PUF designs for different FPGA families and manufacturing technology. Additional, in this paper we proposed three PUF schemes based in the combination of two previous PUFs designs: BUT and LUT. All schemes were implemented and evaluated with main PUF metrics, on Spartan-3E, Spartan-6, and Virtex-5. An analysis of the results allows us to determine which FPGA platform have good behavior and what is the performance impact by the environmental variations.

关键词： environmental factors field programmable gate arrays integrated circuit reliability BUT LUT PUF designs Spartan-3E Spartan-6 Virtex-5 Xilinx FPGAs families bit aliasing environmental variations manufacturing technology performance evaluation physical unclonable function constructions reliability Field programmable gate arrays Latches Mathematical model Measurement Reliability Table lookup Field programmable gate arrays Table lookup Manufacturing technology Latch Device Component integrated circuit reliability Performance Evaluation Mathematical Model Lower Urinary Tract Symptoms

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Educating Hardware Design - From Boolean Equations to Massively Parallel Computing Systems 9

Educating Hardware Design - From Boolean Equations to Massiv...

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9th southern conference on programmable logic (spl)

作者： Knodel, Oliver Zabel, Martin Lehmann, Patrick Spallek, Rainer G. Tech Univ Dresden Dept Comp Sci D-01062 Dresden Germany

ISBN: (纸本)9781479968480

the future of hardware development lies in massively parallel hardware architectures as used in embedded as well as high-performance systems, for instance streaming-based, real-time and database applications. Especially field-programmable gate arrays provide a platform for the rapid development of integrated circuits and the accompanied software. For reasons of energy efficiency, it is increasingly important to tailor hardware directly to the application. As such systems are very complex, the training of engineers has to start early. Furthermore, the usual curricula in computer science and electrical engineering teach only basic skills. In this paper we present lectures and especially practical FPGA design courses for bachelor and master students. We introduce a selection of individual projects, which were realized by students in practical courses. With examples from final bachelor projects and master theses we demonstrate the quality of education and its integration into current research. We describe possible improvements of labs, such as automated test benches and a remote FPGA laboratory for advanced courses.

关键词： Boolean algebra educational courses electronic engineering education embedded systems field programmable gate arrays further education logic design parallel architectures Boolean equations FPGA design courses advanced courses automated test benches bachelor students computer science education quality electrical engineering field-programmable gate arrays final bachelor projects hardware design hardware development high-performance systems integrated circuits massively parallel computing systems massively parallel hardware architecture master students master theses practical courses remote FPGA laboratory Computer architecture Computers Educational institutions Field programmable gate arrays Hardware System-on-chip Field programmable gate arrays computer hardware design Embedded systems Advanced Courses Continuing Education electrical engineering Computer hardware computer science system-on-chip parallel computing system Parallel architectures logic design Computer Architecture Boolean algebra Educational institutions

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RO-based PRNG: FPGA implementation and stochastic analysis 9

RO-based PRNG: FPGA implementation and ...

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9th southern conference on programmable logic (spl)

作者： De Micco, Luciana Antonelli, Maximiliano Larrondo, Hilda A. Boemo, Eduardo Natl Univ Mar del Plata Sch Engn Dept Phys RA-7600 Mar Del Plata Buenos Aires Argentina Natl Univ Mar del Plata Sch Engn Dept Elect RA-7600 Mar Del Plata Buenos Aires Argentina Consejo Nacl Invest Cient & Tecn RA-1033 Buenos Aires DF Argentina Univ Autonoma Madrid Digital Syst Lab E-28049 Madrid Spain

ISBN: (纸本)9781479968480

this paper deals with the use of Ring Oscillators (ROs) as pseudo random number generators (PRNG). the design, made for ALTERA Cyclone III (c), using low level primitives is explained. Two relevant characteristics of a PRNG are considered to validate the design: 1) the equiprobability of all possible outcomes and 2) the statistical independence of consecutive values. In this work these properties are measured via Information theory Quantifiers. A dual entropy plane is used to represent the time series and easily visualize the results obtained with different configurations. the quality is also compared with other available PRNGs by means of the dual entropy plane. Our method constitutes an effective reduction of the complete analysis made with test suites like DIEHARD or NIST.

关键词： entropy field programmable gate arrays oscillators random number generation Altera Cyclone III DIEHARD test suite FPGA implementation NIST test suite RO-based PRNG dual entropy plane equiprobability field programmable gate array information theory quantifier low level primitive pseudorandom number generator ring oscillator statistical independence stochastic analysis Entropy Field programmable gate arrays Hardware Histograms Inverters Noise Table lookup Field programmable gate arrays equiprobability stochastic analysis entropy Table lookup Pseudorandom number generator Ring oscillators pseudorandom number generation Inventors histograms Oscillators Computer hardware Noise

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FPGA Implementation of a FEC Decoding Subsystem for a DVB-S2 Receiver 9

FPGA Implementation of a FEC Decoding Subsystem for a DVB-S2...

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9th southern conference on programmable logic (spl)

作者： Alves, Denise C. Chaves, Cesar G. de Lima, Eduardo R. da Silva, Gabriel S. Queiroz, Augusto F. R. Eldorado Res Inst Campinas SP Brazil Univ Politecn Valencia Valencia Spain

ISBN: (纸本)9781479968480

this paper presents the implementation of a FEC decoding subsystem for a DVB-S2 compliant receiver. the FEC decoder is composed by three blocks: De-interleaver, LDPC and BCH decoders, and its main goal is correcting the bits that were corrupted by the channel during transmission. the DVB-S2 standard defines several coding schemes and interleaving methods for protecting the data, and all the configurations were considered in this implementation. this work presents the structure and functionality of the FEC subsystem, the platform that was assembled for measuring its performance, and the FPGA synthesis and BER performance results.

关键词： data protection decoding digital video broadcasting field programmable gate arrays forward error correction parity check codes BCH decoders BER performance Bose-Chaudhuri-Hocquenghem decoder DVB-S2 compliant receiver FEC decoding subsystem FPGA synthesis LDPC decoders de-interleaver decoders digital video broadcasting system for satellite broadcasting and unicasting forward error correction subsystem low density parity check code Bit error rate Decoding Digital video broadcasting Forward error correction Parity check codes Signal to noise ratio Standards digital video broadcasting parity check codes Forward error correction computer information security Data Security DECODING Field programmable gate arrays bit error rate performance low density parity check codes signal to noise ratios Bit error rate DVB-S2 FEC Regimen

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Hardware-accelerated spike train generation for neuromorphic image and video processing 9

Hardware-accelerated spike train generation for neuromorphic...

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9th southern conference on programmable logic (spl)

作者： Iakymchuk, T. Rosado-Munoz, A. Bataller-Mompean, M. Guerrero-Martinez, J. F. Frances-Villora, J. V. Wegrzyn, M. Adamski, M. Univ Valencia GPDS Dept Elect Engn ETSE E-46100 Valencia Spain Univ Zielona Gora Inst Comp Engn & Elect PL-65246 Zielona Gora Poland

ISBN: (纸本)9781479968480

Recent studies concerning Spiking Neural Networks show that they are a powerful tool for multiple applications as pattern recognition, image tracking, and detection tasks. the basic functional properties of SNN reside in the use of spike information encoding as the neurons are specifically designed and trained using spike trains. We present a novel and efficient frequency encoding algorithm with Gabor-like receptive fields using probabilistic methods and targeted to FPGA for online processing. the proposed encoding is versatile, modular and, when applied to images, it is able to perform simple image transforms as edge detection, spot detection or removal, and Gabor-like filtering without any further computation requirements. the algorithm is implemented in FPGA and ready to be used in embedded systems, being capable of processing images or video stream up to 40 megapixel per second per single core. Results show an improvement in hardware occupation and encoding speed up to 2.5x over existing state of the art implementations.

关键词： Gabor filters edge detection feature extraction field programmable gate arrays filtering theory neural nets object detection probability video coding video streaming FPGA Gabor-like receptive fields detection task frequency encoding algorithm hardware-accelerated spike train generation image stream processing image tracking image transforms neuromorphic image processing neuromorphic video processing pattern recognition probabilistic methods spike information encoding spike trains spiking neural networks spot detection spot removal video stream processing Biomembranes Electric potential Encoding Hardware Neurons Radio frequency Visualization Field programmable gate arrays Edge detection image tracking Membrane, biological Neural network Gabor filters filtering theory potential Object detection Video streaming radiofrequency Computer hardware Pattern recognition Video coding graph transformation

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