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international conference on hardware/software codesign and system synthesis (codes)

作者： Wei Jiang Liugen Xiu Jinyu Zhan Ke Jiang School of Information & Software Engineering University of Electronic Science & Technology of China China Research and Engineering Department Veoneer Sweden

We present a system-level co-design approach for security-critical real-time systems to resist fault injection attack. We focus on protecting the encryption/decryption of confidential messages over the internal communication in distributed realtime systems. To achieve the goal, we identify ten mechanisms of Fault Detection and Correction (FDC) and measure their corresponding time overheads and hardware overheads. We then make efforts to search for the best FDC schemes for protecting the message communication without violating the application deadline and hardware budget. We propose an efficient heuristic based on multi-objective evolutionary algorithms, which obtains better solutions with lower time complexity. Experiments demonstrate the superiority of the proposed technique.

关键词： Field programmable gate arrays Task analysis Cryptography Real-time systems Fault detection Resists

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Work-in-Progress: Hierarchical Ensemble Learning for Resource-Aware FPGA Computing

Work-in-Progress: Hierarchical Ensemble Learning for Resourc...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Hongfei Wang Jianwen Li Kun He Wenjie Cai School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

Recent years witness the rapid development in hardware/software codesign that integrates machine learning (ML) models with hardware systems [1]-[4]. Despite the booming trend in building neuromorphic computing systems [2], decision trees still attract much attention in ML communities, from both software [5], [6] and hardware [1], [7], [8] approaches. A single tree model may not be as accurate as desired. One effective way to remedy this is to apply ensemble methods [5]-[7], [9]-[11], such as the Random Forest (RF) [5]. Larger tree ensembles typically improve accuracy, but demand more computation resources, especially for hardware implementation. Many methods have been proposed to address this issue. The motivation arouses from the fact that tree models usually demands much less computation resource comparing to neural networks, making them extremely potential for wearable devices and embedded systems at the edge nodes of the IoT [7], [11], [12]. Moreover, due to their inherent structures, tree ensembles are ideal for exploiting the computational parallelism on FPGA [1], [4], [7]-[9], [11], [13].

关键词： Radio frequency Vegetation hardware Field programmable gate arrays Forestry Minimization Computational modeling

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Work-in-Progress: A Chip-Level Security Framework for Assessing Sensor Data Integrity

Work-in-Progress: A Chip-Level Security Framework for Assess...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Taimour Wehbe Vincent J. Mooney David C. Keezer Georgia Institute of Technology Atlanta Georgia USA

The continuously increasing inter-connectivity of sensor nodes that form the basis of the Internet-of-Things results in new avenues of attack exploitable by adversaries to maliciously modify data captured by these nodes. In this work, we present a framework for detecting malicious hardware alterations that attempt to attack state-of-the-art microchips that form these sensor nodes. Specifically, we focus on extremely small hardware Trojans (HTs) that attempt to modify sensor data right away as the data is received on a state-of-the-art chip fabricated in an untrusted facility. We present a dual-chip approach composed of an untrusted state-of-the-art prover chip and a trusted verifier chip, where the verifier continuously challenges the prover at run-time to ensure correct operation and assess the integrity of the captured data. Our preliminary analysis of the proposed mechanism shows that HT attacks anywhere on the untrusted state-of-the-art chip are detected and flagged preventing maliciously altered data to be transmitted out of the sensor node.

关键词： hardware Trojan horses Integrated circuits Data integrity Embedded systems Drugs

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An Ultra-Low Energy Human Activity Recognition Accelerator for Wearable Health Applications

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ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 49-49页

作者： Bhat, Ganapati Tuncel, Yigit An, Sizhe Lee, Hyung Gyu Ogras, Umit Y. Arizona State Univ Sch Elect Comp & Energy Engn Tempe AZ 85287 USA Daegu Univ Sch Comp & Commun Engn Daegu 38453 South Korea

Human activity recognition (HAR) has recently received significant attention due to its wide range of applications in health and activity monitoring. The nature of these applications requires mobile or wearable devices with limited battery capacity. User surveys show that charging requirement is one of the leading reasons for abandoning these devices. Hence, practical solutions must offer ultra-low power capabilities that enable operation on harvested energy. To address this need, we present the first fully integrated custom hardware accelerator (HAR engine) that consumes 22.4 mu J per operation using a commercial 65 nm technology. We present a complete solution that integrates all steps of HAR, i.e., reading the raw sensor data, generating features, and activity classification using a deep neural network (DNN). It achieves 95% accuracy in recognizing 8 common human activities while providing three orders of magnitude higher energy efficiency compared to existing solutions.

关键词： Human activity recognition wearable electronics flexible hybrid electronics hardware accelerator low-power design health monitoring

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Special Session Paper: An Efficient hardware Design for Cerebellar Models using Approximate Circuits 12

Special Session Paper: An Efficient Hardware Design for Cere...

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international conference on hardware/software codesign and system synthesis (codes+isss)

作者： Jiang, Honglan Liu, Leibo Han, Jie Univ Alberta Edmonton AB Canada Tsinghua Univ Inst Microelect Beijing Peoples R China

ISBN: (纸本)9781450351850

The superior controllability of the cerebellum has motivated extensive interest in the development of computational cerebellar models. Many models have been applied to the motor control and image stabilization in robots. Often computationally complex, cerebellar models have rarely been implemented in dedicated hardware. Here, we propose an efficient hardware design for cerebellar models using approximate circuits with a small area and a low power. Leveraging the inherent error tolerance in the cerebellum, approximate adders and multipliers are carefully evaluated for implementations in an adaptive filter based cerebellar model to achieve a good tradeoff in accuracy and hardware usage. A saccade system, whose vestibulo-ocular reflex (VOR) is controlled by the cerebellum, is simulated to show the applicability and effectiveness of the proposed design. Simulation results show that the approximate cerebellar circuit achieves a similar accuracy as an exact implementation, but it saves area by 29.7% and power by 37.3%.

关键词： Cerebellar model approximate circuits multiplier adder

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Work-in-Progress: Heterogeneous Redundancy to Address Performance and Cost in Multi-core SIMT 12

Work-in-Progress: Heterogeneous Redundancy to Address Perfor...

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international conference on hardware/software codesign and system synthesis (codes+isss)

作者： Naghashi, M. Mozafari, S. H. Hessabi, S. Sharif Univ Technol Tehran Iran McGill Univ Montreal PQ Canada

ISBN: (纸本)9781450351850

As manufacturing processes scale to smaller feature sizes and processors become more complex, it is becoming challenging to have fabricated devices that operate according to their speciication in the irst place: yield losses are mounting [3]. In this work, we investigate adding heterogeneous hot redundancy (i.e., the architecture of redundant hot cores is diferent from the baseline cores) to improve the cost and performance of multicore single-instruction, multiple-thread (SIMT) architectures. We propose to utilize x86 out of order (OoO) cores as redundancy in SIMT processors. In this case, dice with unused functional redundancies can beneit from two types of processing cores (OoO and SM).

关键词： Manufacturability system-level design redundancy

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Enhanced Resilient Sensor Attack Detection Using Fusion Interval and Measurement History 18

Enhanced Resilient Sensor Attack Detection Using Fusion Inte...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Kang Yang Rui Wang Yu Jiang Chenxia Luo Yong Guan Xiaojuan Li Zhiping Shi College of Information Engineering Capital Normal University Beijing China School of Software Tsinghua University Beijing China

ISBN: (纸本)9781538655627

For the Cyber-Physical systems which are equipped with multiple sensors that measure the same physical variables, some of the sensors may be subject to malicious attacks and provide the wrong measurements to the controller, resulting in an unsafe state of the system. Although there are several methods for detecting sensor attacks, they may not work well when an attacker manipulates the sensor output very slightly or infrequently over a period of time, e.g., stealth attacks. To address this problem, we take the system dynamics model into account, and propose a novel sensor attack detection algorithm based on historical measurements and fusion intervals. The core idea is to build different fault models for different sensors, add a virtual sensor to use pairwise inconsistencies between two sensors to identify attacks. Finally, we validate the performance of the algorithm on real measurements obtained from the LEGO EV3 ground vehicle, and the results show that the proposed method outperforms state-of-the-art algorithm, especially for stealth attacks, with about 92% promotion in attack detection and identification rate.

关键词： Robot sensing systems Transient analysis Silicon Detectors Security Time measurement Cyber-physical systems

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Work-in-Progress: Remote Detection of Unauthorized Activity via Spectral Analysis 12

Work-in-Progress: Remote Detection of Unauthorized Activity ...

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international conference on hardware/software codesign and system synthesis (codes+isss)

作者： Karabacak, Fatih Ogras, Umit Ozev, Sule Arizona State Univ Sch ECEE Tempe AZ 85281 USA

ISBN: (纸本)9781450351850

Unauthorized hardware or firmware modifications, known as trojans, can steal information, drain the battery, or damage IoT devices. This paper presents a stand-off self-referencing technique for detecting unauthorized activity. The proposed technique processes involuntary electromagnetic emissions on a separate hardware, which is physically decoupled from the device under test. When the device enter the test mode, it runs a predefined application repetitively with a fixed period. The periodicity ensures that the spectral electromagnetic power of the test application concentrates at known frequencies, leaving the remaining frequencies within the operation bandwidth at the noise level. Any deviations from the noise level for these unoccupied frequency locations indicates the presence of unknown (unauthorized) activity. Experiments based on hardware measurements show that the proposed technique achieves close to 100% detection accuracy at up to 120 cm distance.

关键词： IoT Security hardware/Firmware Trojan Detection EM Emission

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Work-in-Progress: A PV Aware Data Placement Scheme for Read Performance Improvement on LDPC based Flash Memory 12

Work-in-Progress: A PV Aware Data Placement Scheme for Read ...

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international conference on hardware/software codesign and system synthesis (codes+isss)

作者： Li, Qiao Shi, Liang Di, Yejia Du, Yajuan Wu, Kaijie Xue, Chun Jason Zhuge, Qingfeng Sha, Edwin H-M. Chongqing Univ Coll Comp Sci Chongqing Peoples R China City Univ Hong Kong Dept Comp Sci Hong Kong Hong Kong Peoples R China

ISBN: (纸本)9781450351850

This paper proposes to improve read performance of LDPC based flash memory by exploiting process variation (PV). The work includes three parts. First, a block grouping approach is proposed to classify the flash blocks based on their reliability. Second, based on the grouping approach, a read data placement scheme is proposed, which is designed to place read-hot data on flash blocks with high reliability. However, simply placing read-hot data to high reliable blocks conflicts with recent PV-aware wear leveling schemes. In the third part of the work, a grouping partition scheme is proposed to limit the number of high reliable blocks for read-hot data. In this case, read performance can be well improved with little impact on the lifetime improvement.

关键词： Reliability Parity check codes Time factors Sensors Error correction codes Flash memories Computer science

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Work-in-Progress: Furion: Alleviating Overheads for Deep Learning Framework On Single Machine

Work-in-Progress: Furion: Alleviating Overheads for Deep Lea...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Lihui Jin Chao Wang Lei Gong Chongchong Xu Yahui Hu Luchao Tan Xuehai Zhou University of Science and Technology of China

Deep learning has been successful at solving many kinds of tasks. hardware accelerators with high performance and parallelism have become mainstream to implement deep neural networks. In order to increase hardware utilization, multiple applications will share the same compute resource. However, different applications may use different deep learning frameworks and occupy different amounts of resources. If there are no scheduling platforms that are compatible with different frameworks, resources competition will result in longer response time, run out of memory, and other errors. When the resources of the system cannot satisfy all the applications at the same time, application switching overhead will be excessive without reasonable resource management strategy. In this paper, we propose Furion - a middleware alleviates overheads for deep learning framework on a single machine. Furion schedules tasks, overlaps the execution of different computing resource, and batches unknown inputs to increase the hardware accelerator utilization. It dynamically manages memory usage for each application to alleviate the overhead of application switching and make a complex model enable implement in a low-end GPU. Our experiment proved that Furion achieves 2.2x-2.7x speedup on the GTX1060.

关键词： hardware Task analysis Graphics processing units Switches Neural networks Throughput

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