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检索条件"任意字段=2014 International Conference on Hardware/Software Codesign and System Synthesis, CODES ISSS 2014"

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Work-in-progress: IR-level Annotation strategy dealing with aggressive loop optimizations for performance estimation in native simulation 12

Work-in-progress: IR-level Annotation strategy dealing with ...

引用

12th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, codes 2017

作者： Matoussi, Omayma Pétrot, Frédéric TIMA Laboratory Grenoble INP France

ISBN: (纸本)9781450351850

Originally developed for purely functional verification of software, native or host compiled simulation [6] has gained momentum, thanks to its considerable speedup compared to instruction set simulation (ISS). To obtain a performance model of the software, non-functional information is computed from the target binary code using low-level analysis and back-annotated into the high-level code used to generate it. This annotated functional model is then natively compiled and executed on the host machine for fast software timing [8] estimations. Back-annotating at the right place needs a mapping between the binary instructions and the high-level code statements. So, it is necessary to decide at which stage of the software compilation process the information is back-annotated. There are three possibilities: in the original source code ([7]), in the host binary code ([3]), or in the compiler intermediate representation (IR) ([8], [2]). As compilers perform many optimizations to enhance software performance, the source code and the binary code structures may be radically different. In this work, we define a mapping approach between the compiler's IR and the binary control flow graph (CFG) when a high-level of compiler optimizations (eg. O3 in GCC) is used. Our approach handles aggressive compiler optimizations such as loop unrolling without having to introduce any modification to the compiler. © 2017 ACM.

关键词： Binary codes

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Optimal Functional-Unit Assignment and Buffer Placement for Probabilistic Pipelines 16

Optimal Functional-Unit Assignment and Buffer Placement for ...

引用

international conference on hardware/software codesign and system synthesis (codes+isss)

作者： Jiang, Weiwen Sha, Edwin H. -M. Zhuge, Qingfeng Chen, Xianzhang Chongqing Univ Coll Comp Sci Chongqing Peoples R China

ISBN: (纸本)9781450344838

Applications, such as streaming applications, modeled by task graphs can be efficiently executed in a pipelined fashion. In synthesizing application-specific heterogeneous pipelined systems, where to place buffers (called buffer placement) and what type of functional units to execute each task (called functional assignment) are two critical problems. In reality, the execution time of each task may not be fixed, which makes the above two problems much more challenging. In this paper, we model the execution time of each task on different types of functional units as a random variable. Our objective is to obtain the optimal functional assignment and buffer placement, such that the resultant pipeline can satisfy the timing requirement with the minimum cost under the guaranteed confidence probability. This paper presents efficient algorithms to achieve the objective. Experiments show that other techniques cannot find any feasible solutions in many cases while ours can. Even for the cases where they can find feasible solutions, our algorithms achieve the minimum cost which gives a significant reduction on the total cost, compared with existing techniques.

关键词： High-level synthesis application-specific system optimal algorithms probabilistic scenario

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Efficient virtual memory sharing via on-accelerator page table walking in heterogeneous embedded SoCs

Efficient virtual memory sharing via on-accelerator page tab...

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ACM Transactions on Embedded Computing systems

作者： Vogel, Pirmin Kurth, Andreas Weinbuch, Johannes Marongiu, Andrea Benini, Luca Integrated Systems Laboratory ETH Zurich Gloriastrasse 35 Zurich8092 Switzerland Electrical Electronic and Information Engineering Department University of Bologna Viale Risorgimento 2 Bologna40126 Italy

Shared virtual memory is key in heterogeneous systems on chip (SoCs) that combine a general-purpose host processor with a many-core accelerator, both for programmability and performance. In contrast to the fullblown, hardware-only solutions predominant in modern high-end systems, lightweight hardware-software co-designs are better suited in the context of more power- and area-constrained embedded systems and provide additional benefits in terms of flexibility and predictability. As a downside, the latter solutions require the host to handle in software synchronization in case of page misses as well as miss handling. This may incur considerable run-time overheads. In this work, we present a novel hardware-software virtual memory management approach for many-core accelerators in heterogeneous embedded SoCs. It exploits an accelerator-side helper thread concept that enables the accelerator tomanage its virtualmemory hardware autonomously while operating cache-coherently on the page tables of the user-space processes of the host. This greatly reduces overhead with respect to host-side solutions while retaining flexibility. We have validated the design with a set of parameterizable benchmarks and real-world applications covering various application domains. For purely memory-bound kernels, the accelerator performance improves by a factor of 3.8 compared with host-based management and lies within 50% of a lower-bound ideal memory management unit. © 2017 ACM.

关键词： Memory management units Acceleration Benchmarking Computer operating systems Embedded systems hardware hardware software codesign Linux Physical addresses system on chip Heterogeneous systems High end systems Many core accelerators Novel hardware Programmability Shared virtual memory Virtual memory Virtual memory management

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Enabling the High Level synthesis of Data Analytics Accelerators 16

Enabling the High Level Synthesis of Data Analytics Accelera...

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international conference on hardware/software codesign and system synthesis (codes+isss)

作者： Minutoli, Marco Castellana, Vito Giovanni Tumeo, Antonino Lattuada, Marco Ferrandi, Fabrizio Pacific Northwest Natl Lab High Performance Comp Richland WA 99352 USA Politecn Milan Dipartimento Elettron Informaz & Bioingn I-20132 Milan Italy

ISBN: (纸本)9781450344838

Conventional High Level synthesis (HLS) tools mainly target compute intensive kernels typical of digital signal processing applications. We are developing techniques and architectural templates to enable HLS of data analytics applications. These applications are memory intensive, present fine-grained, unpredictable data accesses, and irregular, dynamic task parallelism. We discuss an architectural template based around a distributed controller to efficiently exploit thread level parallelism. We present a memory interface that supports parallel memory subsystems and enables implementing atomic memory operations. We introduce a dynamic task scheduling approach to efficiently execute heavily unbalanced workload. The templates are validated by synthesizing queries from the Lehigh University Benchmark (LUBM), a well know SPARQL benchmark.

关键词： High level synthesis

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A novel emulation model of the cardiac conduction system

A novel emulation model of the cardiac conduction system

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作者： Andalam, Sidharta Allen, Nathan Malik, Avinash Roop, Partha S. Trew, Mark University of Auckland Private Bag 92019 Auckland1142 New Zealand

Models of the cardiac conduction system are usually at two extremes: (1) high fidelity models with excellent precision but lacking a real-time response for emulation (hardware in the loop simulation);or (2) models amenable for emulation, but that do not exhibit appropriate dynamic response, which is necessary for arrhythmia susceptibility. We introduce two abstractions to remedy the situation. The first abstraction is a new cell model, which is a semi-linear hybrid automata. The proposed model is as computationally efficient as current state-of-the-art cell models amenable for emulation. Yet, unlike these models, it is also able to capture the dynamic response of the cardiac cell like the higher-fidelity models. The second abstraction is the use of smooth-tokens to develop a new path model, connecting cells, which is efficient in terms of memory consumption. Moreover, the memory requirements of the path model can be statically bounded and are invariant to the emulation step size. Results show that the proposed semi-linear abstraction for the cell reduces the execution time by up to 44%. Furthermore, the smooth-tokens based path model reduces the memory consumption by 40 times when compared to existing path models. This paves the way for the emulation of complex cardiac conduction systems, using hardware code-generators. © 2017 ACM.

关键词： Cells

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GPU performance estimation using software rasterization and machine learning

GPU performance estimation using software rasterization and ...

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作者： O'Neal, Kenneth Brisk, Philip Abousamra, Ahmed Waters, Zack Shriver, Emily University of California Riverside Winston Chung Hall RiversideCA92521 United States Intel Corporation 2501 NE Century Blvd HillsboroOR97124 United States

This paper introduces a predictive modeling framework to estimate the performance of GPUs during presilicon design. Early-stage performance prediction is useful when simulation times impede development by rendering driver performance validation, API conformance testing and design space explorations infeasible. Our approach builds a Random Forest regression model to analyze DirectX 3D workload behavior when executed by a software rasterizer, which we have extended with a workload characterizer to collect further performance information via program counters. In addition to regression models, this work produces detailed feature rankings which can provide valuable architectural insight, and accurate performance estimates for an Intel integrated Skylake generation GPU. Our models achieve reasonable out-of-sample-error rates of 14%, with an average simulation speedup of 327x. © 2017 ACM.

关键词： Graphics processing unit

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Efficient Design Space Exploration by Knowledge Transfer 16

Efficient Design Space Exploration by Knowledge Transfer

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international conference on hardware/software codesign and system synthesis (codes+isss)

作者： Li, Dandan Wang, Senzhang Yao, Shuzhen Liu, Yu-Hang Cheng, Yuanqi Sun, Xian-He Beihang Univ Sch Comp Sci & Engn Beijing Peoples R China Nanjing Univ Aeronaut & Astronaut Coll Comp Sci & Technol Nanjing Jiangsu Peoples R China Collaborat Innovat Ctr Novel Software Technol & I Nanjing Jiangsu Peoples R China Chinese Acad Sci Inst Comp Technol Beijing Peoples R China IIT Dept Comp Sci Chicago IL 60616 USA

ISBN: (纸本)9781450344838

Due to the exponentially increasing size of design space of microprocessors and time-consuming simulations, predictive models have been widely employed in design space exploration (DSE). Traditional approaches mostly build a program-specific predictor that needs a large number of program-specific samples. Thus considerable simulation cost is required for each program. In this paper, we study the novel problem of transferring knowledge from the labeled samples of previous programs to help predict the responses of the new target program whose labeled samples are very sparse. Inspired by the recent advances of transfer learning, we propose a transfer learning based DSE framework TrDSE to build a more efficient and effective predictive model for the target program with only a few simulations by borrowing knowledge from previous programs. Specifically, TrDSE includes two phases: 1) clustering the programs based on the proposed orthogonal array sampling and the distribution related features, and 2) with the guidance of clustering results, predicting the responses of configurations in design space of the target program by a transfer learning based regression algorithm. We evaluate the proposed TrDSE on the benchmarks of SPEC CPU 2006 suite. The results demonstrate that the proposed framework is more efficient and effective than state-of-art DSE techniques.

关键词： Design space exploration Processor design Knowledge transfer

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An Accurate and Flexible Early Memory system Power Evaluation Approach Using a Microcomponent Method 16

An Accurate and Flexible Early Memory System Power Evaluatio...

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international conference on hardware/software codesign and system synthesis (codes+isss)

作者： Chen, Chi-Kang Wu, Hsin-I Hsiao, Chi-Ting Tsay, Ren-Song Natl Tsing Hua Univ Dept Comp Sci Hsinchu Taiwan Ind Technol Res Inst Hsinchu Taiwan

ISBN: (纸本)9781450344838

As energy efficiency has become a primary concern, system designers have greater need for a flexible and highly accurate power estimation method for evaluating different architecture options. Since memory is an increasingly dominant power consumer, we reexamine existing memory power models and propose a highly efficient microcomponent-based approach with data-aware refinement for accurate system-level power estimations. The key contribution of our approach is that the proposed microcomponent method allows designers to use flexible architecture compositions. Our approach identifies the common microcomponents used by internal memory commands and accurately pre-calibrates the power consumption pattern of each microcomponent. We decompose target design architectures into these microcomponents to easily derive accurate power estimates. To achieve very high accuracy, we consider the data variation effect by leveraging the fact that memory circuit is mainly doing data passing and hence a simple interpolation technique can further boost accuracy. Our experiments show that the proposed approach produces accurate results of less than 2% error rate in average for system power analysis.

关键词： Energy efficiency

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How to Enable software Isolation and Boost system Performance with Sub-block Erase over 3D Flash Memory 16

How to Enable Software Isolation and Boost System Performanc...

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international conference on hardware/software codesign and system synthesis (codes+isss)

作者： Chang, Hsin-Yu Ho, Chien-Chung Chang, Yuan-Hao Chang, Yu-Ming Kuo, Tei-Wei Macronix Int Co Ltd Hsinchu Taiwan Acad Sinica Inst Informat Sci Taipei Taiwan Acad Sinica Res Ctr Informat Technol Innovat Taipei Taiwan Natl Taiwan Univ Dept Comp Sci & Informat Engn Taipei Taiwan

ISBN: (纸本)9781450344838

The write amplification problem deteriorates as the block size of modern flash-memory chips keeps increasing. Without the careful garbage collection, significant live-page copying might even worsen the reliability problem, that is already severe to 3D flash memory. In this work, we propose a sub-block erase design to not only alleviate the write amplification problem by reducing live-page copying but also improve the system reliability with a software isolation strategy. In particular, sub-blocks are carefully allocated to satisfy write requests so as to reduce disturbance by using free or invalid sub-blocks as isolation layers among sub-blocks, without additional hardware cost and capacity loss. A series of experiments were conducted to evaluate the capability of the proposed design. The results show that the proposed design is very effective in improving the system performance by reducing garbage collection overheads and in improving the device reliability/lifetime.

关键词： Flash memory

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Conquering MPSoC Complexity with Principles of a Self-Aware Information Processing Factory 16

Conquering MPSoC Complexity with Principles of a Self-Aware ...

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international conference on hardware/software codesign and system synthesis (codes+isss)

作者： Dutt, Nikil Kurdahi, Fadi J. Ernst, Rolf Herkersdorf, Andreas Univ Calif Irvine Ctr Embedded & Cyber Phys Syst Irvine CA 92697 USA Tech Univ Carolo Wilhelmina Braunschweig Braunschweig Germany Tech Univ Munich D-80290 Munich Germany

ISBN: (纸本)9781450344838

We introduce the idea of an Information Processing Factory as a step towards autonomous many-core platforms in Cyber-Physical systems (CPS) and the Internet of Things (IoT). It represents a paradigm shift in platform design moving long term, with robust and independent platform operation in the focus of platform-centric design rather than existing semiconductor device or software technology, as mostly seen today. Such a refocus is not only needed to prepare for the time when technology scaling comes to an end, but is a necessity to manage complexity when networked IT systems not only by far outnumber humans but when their complexity by far exceeds that of human societies. While such applications complexity growth is visible to large parts of the society, and is publicly discussed, it is important to note that the complexity growth equally affects the platforms (computers, communication, storage, etc.) which enable such growing applications. This challenge is partly addressed by the new areas of Cyber-Physical systems and the Internet-of-Things, but the changing challenges to the operation of complex microelectronic systems is mostly left to computer and software architects, and to semiconductor technology. This perspective paper motivates the necessity for a paradigm shift in IT system design and its application to autonomous systems as a main application.

关键词： Self-awareness system-on-Chip cyber-physical systems

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