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检索条件"任意字段=2014 International Conference on Hardware/Software Codesign and System Synthesis, CODES ISSS 2014"

共 593 条记录，以下是161-170 订阅

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Scalable and Realistic Benchmark synthesis for Efficient NoC Performance Evaluation: A Complex Network Analysis Approach 16

Scalable and Realistic Benchmark Synthesis for Efficient NoC...

引用

international conference on hardware/software codesign and system synthesis (codes+isss)

作者： Xue, Yuankun Bogdan, Paul Univ Southern Calif 3740 McClintock Ave Los Angeles CA 90007 USA

ISBN: (纸本)9781450344838

The complexity of the design-space exploration of large-scale NoCs is exacerbated not only by the ever-increasing number of cores, but also by the increased runtime uncertainties in both the scale and task structure of the emerging applications. Consequently, it is crucial to develop rigorous mathematical frameworks for capturing the task dependencies of varied applications to foster the generation of realistic benchmarks that can guide the NoC design. However, the current NoC benchmark suites either lack portability and poorly scale as they require intensive development efforts on specific architectures and simulation time, or are synthesized based on purely stochastic models that are disconnected with real applications, which may easily lead to biased and/or delayed design choices. To overcome these drawbacks, we propose a benchmark synthesis framework that i) not only allows extraction of dynamical task dependencies of the application and synthesize traffic workloads spatio-temporally consistent with realistic traffic behavior, ii) but can also be easily scaled by the proposed complex network inspired algorithm for large benchmark generation while preserving key structural features that governs application communication behaviors. We validate the proposed framework on a large-scale simulation environment by running a set of real applications. Experimental results show that the synthesized benchmarks respect the traffic patterns of the original applications and preserve key features of application task structures.

关键词： Network-on-chip

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2013 international conference on hardware/software codesign and system synthesis, codes+isss 2013

2013 International conference on hardware/software codesign ...

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11th ACM/IEEE international conference on hardware/software codesign and system synthesis, codes+isss 2013

ISBN: (纸本)9781479914173

The proceedings contain 37 papers. The topics discussed include: embedded supercomputing in FPGAs with the VectorBlox MXP matrix processor;WHISK: an uncore architecture for dynamic information flow tracking in heterogeneous embedded SoCs;a reconfigurable real-time SDRAM controller for mixed time-criticality systems;DHeating: dispersed heating repair for self-healing NAND flash memory;synthesis-friendly techniques for tightly-coupled integration of hardware accelerators into shared-memory multi-core clusters;reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache;pvFPGA: accessing an FPGA-based hardware accelerator in a paravirtualized environment;on the automatic generation of GPU-oriented software applications from RTL IPs;CMSM: an efficient and effective code management for software managed multicores;and learning the optimal operating point for many-core systems with extended range voltage/frequency scaling.

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Time in Cyber-Physical systems 16

Time in Cyber-Physical Systems

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international conference on hardware/software codesign and system synthesis (codes+isss)

作者： Shrivastava, Aviral Derler, Patricia Li Baboud, Ya-Shian Stanton, Kevin Khayatian, Mohammad Andrade, Hugo A. Weiss, Marc Eidson, John Chandhoke, Sundeep Arizona State Univ Tempe AZ 85287 USA Natl Instruments Austin TX USA Intel Corp Santa Clara CA 95051 USA Natl Inst Stand & Technol Gaithersburg MD 20899 USA Univ Calif Berkeley Berkeley CA 94720 USA

ISBN: (纸本)9781450344838

Many modern cyber-physical systems (CPS), especially industrial automation systems, require the actions of multiple computational systems to be performed at much higher rates and more tightly synchronized than is possible with ad hoc designs. Time is the common entity that computing and physical systems in CPS share, and correct interfacing of that is essential to flawless functionality of a CPS. Fundamental research is needed on ways to synchronize clocks of computing systems to a high degree, and on design methods that enable building blocks of CPS to perform actions at specified times. To realize the potential of CPS in the coming decades, suitable ways to specify distributed CPS applications are needed, including their timing requirements, ways to specify the timing of the CPS components (e.g. sensors, actuators, computing platform), timing analysis to determine if the application design is possible using the components, confident top-down design methodologies that can ensure that the system meets its timing requirements, and ways and methodologies to test and verify that the system meets the timing requirements. Furthermore, strategies for securing timing need to be carefully considered at every CPS design stage and not simply added on. This paper exposes these challenges of CPS development, points out limitations of previous approaches, and provides some research directions towards solving these challenges.

关键词： Cyber Physical system

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Edge-TM: Exploiting transactional memory for error tolerance and energy efficiency

Edge-TM: Exploiting transactional memory for error tolerance...

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ACM Transactions on Embedded Computing systems

作者： Papagiannopoulou, Dimitra Marongiu, Andrea Moreshet, Tali Herlihy, Maurice Bahar, R. Iris Department of Electrical and Computer Engineering University of Massachusetts Lowell LowellMA01854 United States Department of Information Technology and Electrical Engineering ETH Zurich Zurich8092 Switzerland College of Engineering Boston University BostonMA02215 United States Department of Computer Science Brown University ProvidenceRI02912 United States School of Engineering Brown University ProvidenceRI02912 United States

Scaling of semiconductor devices has enabled higher levels of integration and performance improvements at the price of making devices more susceptible to the effects of static and dynamic variability. Adding safety margins (guardbands) on the operating frequency or supply voltage prevents timing errors, but has a negative impact on performance and energy consumption. We propose Edge-TM, an adaptive hardware/software error management policy that (i) optimistically scales the voltage beyond the edge of safe operation for better energy savings and (ii) works in combination with a hardware Transactional Memory (HTM)-based error recovery mechanism. The policy applies dynamic voltage scaling (DVS) (while keeping frequency fixed) based on the feedback provided by HTM, which makes it simple and generally applicable. Experiments on an embedded platform show our technique capable of 57% energy improvement compared to using voltage guardbands and an extra 21-24% improvement over existing state-of-the-art error tolerance solutions, at a nominal area and time overhead. © 2017 ACM.

关键词： Energy efficiency Energy conservation Energy utilization Errors hardware Reliability Semiconductor devices Storage allocation (computer) Voltage scaling Dynamic voltage scaling (DVS) Error recovery mechanisms Error tolerance hardware transactional memory Operating frequency Performance improvements Transactional memory Variability

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On-the-fly computing: Self-aware heterogeneous multi-cores

On-the-fly computing: Self-aware heterogeneous multi-cores

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international conference on hardware/software codesign and system synthesis (codes)

作者： Marco Platzner Paderborn University Paderborn Germany

ISBN: (纸本)9781509035908

In this article, we briefly survey the vision and goals of on-the-fly (OTF) computing. Then we turn to heterogeneous multi-cores which, as platforms for OTF computing scenarios, have to support a high dynamics in both the workload and the system state. We argue that concepts and models of self-awareness studied in, for example, psychology, have been successfully transferred to the computing domain and help create systems that can autonomously adapt to changes in their state and environment in order to meet optimization goals and constraints.

关键词： software Engines hardware Actuators Computational modeling Adaptation models Multicore processing

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Big data analytics on heterogeneous accelerator architectures

Big data analytics on heterogeneous accelerator architecture...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Katayoun Neshatpour Avesta Sasan Houman Homayoun Electrical and Computer Engineering Department George Mason University

ISBN: (纸本)9781509035908

In this paper, we present the implementation of big data analytics applications in a heterogeneous CPU+FPGA accelerator architecture. We develop the MapReduce implementation of K-means, K nearest neighbor, support vector machine and Naive Bayes in a Hadoop Streaming environment that allows developing mapper/reducer functions in a non-Java based language suited for interfacing with FPGA-based hardware accelerating environment. We present a full implementation of the HW+SW mappers on the Zynq FPGA platform. A promising speedup as well as energy-efficiency gains of upto 4.5X and 22X is achieved, respectively, in an end-to-end Hadoop implementation.

关键词： Acceleration Field programmable gate arrays hardware Big data Energy efficiency Accelerator architectures

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Security and privacy challenges in IoT-based machine-to-machine collaborative scenarios

Security and privacy challenges in IoT-based machine-to-mach...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Hsin Chung Chen Mohammad Abdullah Al Faruque Pai H. Chou Center for Embedded and Cyber-Physical Systems University of California Irvine CA USA

ISBN: (纸本)9781509035908

Currently, the IoT discussion is focused primarily on the operational phase. This includes how a IoT device behaves, operates, communicates, and interacts with other IoT devices during operation. However, IoT devices and systems have other lifecycle phases before and after operation. This extended abstract provides an overview of how other IoT lifecycle phases (e.g., design and service) can be improved with information feedback and feedforward flows between them. Digital Twins are a new mechanism to manage IoT devices and IoT systems-of-systems throughout their lifecycle. We present our vision on the industrial IoT lifecycle managed and optimized at scale via Digital Twins.

关键词： Security Privacy Collaboration Sensors Entropy Radio frequency hardware

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Fast and cycle-accurate simulation of multi-threaded applications on SMP architectures using hybrid prototyping

Fast and cycle-accurate simulation of multi-threaded applica...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Ehsan Saboori Samar Abdi Concordia University Montreal Canada

ISBN: (纸本)9781509035908

This paper presents a fast and cycle accurate simulation environment for early power-performance analysis of multi-threaded applications targeted to symmetric multiprocessing embedded architectures. Our simulation environment leverages the hybrid prototyping technique, where a lightweight emulation kernel performs logical simulation of multiple identical cores on top of a single physical instance of a core. The technique does not require a detailed timing model of the core hardware because the application threads execute directly on the target core. Previous work on hybrid prototyping supported modeling of only statically scheduled threads, thereby severely limiting its modeling capabilities. In this work, we describe the modeling of dynamic RTOS scheduler as well as hardware interrupts on top of the emulation kernel, in order to support the simulation of unmodified multi-threaded applications. Our experimental results demonstrate the high accuracy, simulation speed and scalability of our hybrid prototyping-based simulation models.

关键词： hardware Multicore processing Kernel Prototypes Emulation Field programmable gate arrays

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Fault injection at host-compiled level with static fault set reduction for SoC firmware robustness testing

Fault injection at host-compiled level with static fault set...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Petra R. Maier Veit Kleeberger Daniel Mueller-Gritschneder Ulf Schlichtmann Technische Universität München Munich Germany Infineon Technologies Neubiberg Germany

ISBN: (纸本)9781509035908

Decreasing hardware reliability makes robust firmware imperative for safety-critical applications. Hence, ensuring correct handling of errors in peripherals is a key objective during firmware design. To adequately support robustness considerations of firmware designers during implementation, an efficient qualitative fault injection method is required. This paper presents a high-speed fault injection technique based on host-compiled firmware simulation that is suitable to analyze the impact of transient faults on firmware behavior. Additionally, fault set reduction by static code analysis avoids unnecessary injection of masked and equivalent faults. Application of the proposed fault injection technique on an industrial safety-relevant automotive system-on-chip (SoC) firmware demonstrates at least three orders of magnitude speedup compared to instruction set level. In addition, a fault set reduction by 78% is achieved. While significantly reducing the required fault injection time, the presented techniques provide as accurate feedback to the designer as existing state-of-the-art approaches.

关键词： Robustness hardware Computer architecture Safety Microprogramming Testing Registers

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Enabling the high level synthesis of data analytics accelerators

Enabling the high level synthesis of data analytics accelera...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Marco Minutoli Vito Giovanni Castellana Antonino Tumeo Marco Lattuada Fabrizio Ferrandi Antonino Tumeo High Performance Computing Pacific Northwest National Laboratory Richland WA USA Dipartimento di Elettronica Informazione e Bioingegneria Politecnico di Milano Milano Italy

ISBN: (纸本)9781509035908

Conventional High Level synthesis (HLS) tools mainly target compute intensive kernels typical of digital signal processing applications. We are developing techniques and architectural templates to enable HLS of data analytics applications. These applications are memory intensive, present fine-grained, unpredictable data accesses, and irregular, dynamic task parallelism. We discuss an architectural template based around a distributed controller to efficiently exploit thread level parallelism. We present a memory interface that supports parallel memory subsystems and enables implementing atomic memory operations. We introduce a dynamic task scheduling approach to efficiently execute heavily unbalanced workload. The templates are validated by synthesizing queries from the Lehigh University Benchmark (LUBM), a well know SPARQL benchmark.

关键词： Resource description framework Databases Data analysis Benchmark testing High level synthesis Parallel processing Dynamic scheduling

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