检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

566 篇 会议
27 篇 期刊文献

馆藏范围

593 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

291 篇 工学
- 284 篇 计算机科学与技术...
- 248 篇 软件工程
- 66 篇 电子科学与技术（可...
- 30 篇 电气工程
- 29 篇 信息与通信工程
- 26 篇 控制科学与工程
- 8 篇 动力工程及工程热...
- 4 篇 机械工程
- 4 篇 光学工程
- 4 篇 材料科学与工程（可...
- 4 篇 建筑学
- 4 篇 土木工程
- 3 篇 安全科学与工程
- 2 篇 力学（可授工学、理...
- 2 篇 仪器科学与技术
- 1 篇 化学工程与技术
- 1 篇 纺织科学与工程
- 1 篇 轻工技术与工程
- 1 篇 航空宇航科学与技...
71 篇 理学
- 48 篇 数学
- 33 篇 系统科学
- 7 篇 统计学（可授理学、...
- 4 篇 物理学
- 1 篇 生物学
43 篇 管理学
- 35 篇 管理科学与工程(可...
- 13 篇 工商管理
- 10 篇 图书情报与档案管...
4 篇 法学
- 3 篇 社会学
- 1 篇 法学
3 篇 经济学
- 3 篇 应用经济学

主题

122 篇 hardware
73 篇 computer archite...
54 篇 embedded system
50 篇 permission
40 篇 application soft...
38 篇 system-on-a-chip
37 篇 embedded systems
35 篇 energy consumpti...
33 篇 algorithm design...
31 篇 computational mo...
28 篇 space exploratio...
28 篇 software
27 篇 field programmab...
24 篇 runtime
23 篇 system-on-chip
22 篇 timing
22 篇 costs
20 篇 delay
19 篇 registers
19 篇 high level synth...

机构

8 篇 center for embed...
6 篇 school of comput...
6 篇 department of co...
5 篇 school of inform...
5 篇 center for embed...
5 篇 institute for in...
4 篇 university of er...
4 篇 department of el...
4 篇 univ elect sci &...
4 篇 nec laboratories...
4 篇 philips research...
3 篇 integrated signa...
3 篇 department of el...
3 篇 department of co...
3 篇 chongqing univ c...
3 篇 philips research...
3 篇 graz university ...
3 篇 arizona state un...
3 篇 univ calif river...
3 篇 politecn torino ...

作者

7 篇 sri parameswaran
7 篇 ogras umit y.
7 篇 parameswaran sri
7 篇 nikil dutt
7 篇 leupers rainer
6 篇 dutt nikil
6 篇 mitra tulika
5 篇 jiang wei
5 篇 pasricha sudeep
5 篇 rolf ernst
5 篇 robert p. dick
5 篇 jinyu zhan
5 篇 gerstlauer andre...
5 篇 tei-wei kuo
5 篇 wei jiang
5 篇 yuan-hao chang
5 篇 rainer leupers
5 篇 zhan jinyu
5 篇 fummi franco
4 篇 takach andres

语言

593 篇 英文

检索条件"任意字段=2014 International Conference on Hardware/Software Codesign and System Synthesis, CODES ISSS 2014"

共 593 条记录，以下是181-190 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

A disturbance-aware sub-block design to improve reliability of 3D MLC flash memory

A disturbance-aware sub-block design to improve reliability ...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Hung-Sheng Chang Yuan-Hao Chang Tei-Wei Kuo Yu-Ming Chang Hsiang-Pang Li Macronix International Co. Ltd. Emerging System Lab. Hsinchu Taiwan R.O.C. Department of Computer Science and Information Engineering National Taiwan University Taipei Taiwan R.O.C. lnstitute of Information Science Academia Sinica Taipei Taiwan R.O.C. Research Center for Information Technology Innovation Academia Sinica Taipei Taiwan R.O.C.

ISBN: (纸本)9781509035908

The reliability problem of modern flash-memory chips quickly deteriorates because of the nature of MLC chips. Although the vertical stacking of storage cells in 3D flash-memory chips dramatically increases the bit density, compared to 2D chips, it also results in severe disturbance problems. In this work, we propose to create sub-blocks in the MTD layer by considering different program disturb resistance patterns, without any hardware cost. In particular, a disturbance-aware sub-block design is proposed to utilize the hotness information of data to further improve the reliability of 3D MLC flash memory by smartly choosing sub-blocks to use when extra information is available from the flash translation layer. The proposed design was evaluated by a series of experiments over traces from SNIA. It was shown that the disturb errors could be reduced by at least 50% under DFTL and BL, i.e., a page-level FTL and a block-level FTL design, compared to the conventional MLC programming designs.

关键词： Three-dimensional displays Reliability engineering Resistance Programming Logic gates Error correction codes

来源：评论

学校读者我要写书评

暂无评论

Efficient design space exploration by knowledge transfer

Efficient design space exploration by knowledge transfer

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Dandan Li Senzhang Wang Shuzhen Yao Yu-Hang Liu Yuanqi Cheng Xian-He Sun School of Computer Science and Engineering Beihang University Beijing China College of Computer Science and Technology Nanjing University of Aeronautics and Astronautics Nanjing China Collaborative Innovation Center of Novel Software Technology and Industrialization Nanjing China Institute of Computing Technology Chinese Academy of Sciences Beijing China Department of Computer Science Illinois Institute of Technology Chicago USA

ISBN: (纸本)9781509035908

Due to the exponentially increasing size of design space of microprocessors and time-consuming simulations, predictive models have been widely employed in design space exploration (DSE). Traditional approaches mostly build a program-specific predictor that needs a large number of program-specific samples. Thus considerable simulation cost is required for each program. In this paper, we study the novel problem of transferring knowledge from the labeled samples of previous programs to help predict the responses of the new target program whose labeled samples are very sparse. Inspired by the recent advances of transfer learning, we propose a transfer learning based DSE framework TrDSE to build a more efficient and effective predictive model for the target program with only a few simulations by borrowing knowledge from previous programs. Specifically, TrDSE includes two phases: 1) clustering the programs based on the proposed orthogonal array sampling and the distribution related features, and 2) with the guidance of clustering results, predicting the responses of configurations in design space of the target program by a transfer learning based regression algorithm. We evaluate the proposed TrDSE on the benchmarks of SPEC CPU 2006 suite. The results demonstrate that the proposed framework is more efficient and effective than state-of-art DSE techniques.

关键词： Predictive models Knowledge transfer Clustering algorithms Feature extraction Prediction algorithms Training data Space exploration

来源：评论

学校读者我要写书评

暂无评论

Human-machine communication for assistive IoT technologies

Human-machine communication for assistive IoT technologies

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Alexandra Porter Md Muztoba Umit Y. Ogras School of Electrical Computer and Energy Engineering Arizona State University

ISBN: (纸本)9781509035908

Despite the phenomenal advances in the computational power and functionality of electronic systems, human-machine interaction has largely been limited to simple control panels, keyboard, mouse and display. Consequently, these systems either rely critically on close human guidance or operate almost independently from the user. An exemplar technology integrated tightly into our lives is the smartphone. However, the term “smart” is a misnomer, since it has fundamentally no intelligence to understand its user. The users still have to type, touch or speak (to some extent) to express their intentions in a form accessible to the phone. Hence, intelligent decision making is still almost entirely a human task. A life-changing experience can be achieved by transforming machines from passive tools to agents capable of understanding human physiology and what their user wants [1]. This can advance human capabilities in unimagined ways by building a symbiotic relationship to solve real world problems cooperatively. One of the high-impact application areas of this approach is assistive internet of things (IoT) technologies for physically challenged individuals. The Annual World Report on Disability reveals that 15% of the world population lives with disability, while 110 to 190 million of these people have difficulty in functioning [1]. Quality of life for this population can improve significantly if we can provide accessibility to smart devices, which provide sensory inputs and assist with everyday tasks. This work demonstrates that smart IoT devices open up the possibility to alleviate the burden on the user by equipping everyday objects, such as a wheelchair, with decision-making capabilities. Moving part of the intelligent decision making to smart IoT objects requires a robust mechanism for human-machine communication (HMC). To address this challenge, we present examples of multimodal HMC mechanisms, where the modalities are electroencephalogram (EEG), speech commands, and mot

关键词： virtualisation control engineering computing decision making electroencephalography human-robot interaction Internet of Things medical computing medical robotics smart phones Virtualization control engineering computing Internet of things Smartphone Human machine interaction medical computing medical robotics Electroencephalography Intelligent decision making decision making hardware motion compensation world population disability

来源：评论

学校读者我要写书评

暂无评论

hardware synthesis from a Recursive Functional Language

Hardware Synthesis from a Recursive Functional Language

引用

IEEE/ACM international conference on hardware/software codesign and system synthesis (codes+isss)

作者： Zhai, Kuangya Townsend, Richard Lairmore, Lianne Kim, Martha A. Edwards, Stephen A. Columbia Univ New York NY 10027 USA

ISBN: (纸本)9781467383219

An Abstraction in hardware description languages stalled at the register-transfer level decades ago, yet few alternatives have had much success, in part because they provide only modest gains in expressivity. We propose to make a much larger jump: a compiler that synthesizes hardware from behavioral functional specifications. Our compiler translates general Haskell programs into a restricted intermediate representation before applying a series of semantics-preserving transformations, concluding with a simple syntax-directed translation to systemVerilog. Here, we present the overall framework for this compiler, focusing on the intermediate representations involved and our method for translating general recursive functions into equivalent hardware. We conclude with experimental results that depict the performance and resource usage of the circuitry generated with our compiler.

关键词： Functional hardware Recursion High-Level synthesis

来源：评论

学校读者我要写书评

暂无评论

A parallelizable approach for mining likely invariants

A parallelizable approach for mining likely invariants

引用

IEEE/ACM international conference on hardware/software codesign and system synthesis (codes+isss)

作者： Danese, Alessandro Piccolboni, Luca Pravadelli, Graziano Univ Verona Str Grazie 15 I-37134 Verona Italy

ISBN: (纸本)9781467383219

A relevant aspect in design analysis and verification is monitoring how logic relations among different variables change at run time. Current static approaches suffer from scalability problems that prevent their adoption on large designs. On the contrary, dynamic techniques scale better from the memory-consumption point of view. However, to achieve a high accuracy, they require to analyse a huge number of ( long) execution traces, which results in time-consuming phases. In this paper, we present a new efficient approach to automatically infer logic relations among the variables of a design implementation. Both a sequential and a GPU-oriented parallel implementation are proposed to dynamically extract likely invariants from execution traces on different time windows. Execution traces composed of millions of simulation instants can be efficiently analysed.

关键词： data mining graphics processing units hardware-software codesign GPU-oriented parallel implementation design analysis design verification dynamic techniques execution traces likely invariants mining logic relations memory-consumption view point parallelizable approach scalability problems sequential parallel implementation static approaches time windows time-consuming phases Accuracy Analytical models Computer architecture Engines Graphics processing units Instruction sets Instruments design analysis instruction sets design verification Time windows hardware/software co-design Computer Architecture Graphics Processing Unit Engines ANALYSIS MODELS data mining Legal Executions time phase Invariant

来源：评论

学校读者我要写书评

暂无评论

The Shift to Multicores in Real-Time and Safety-Critical systems

The Shift to Multicores in Real-Time and Safety-Critical Sys...

引用

IEEE/ACM international conference on hardware/software codesign and system synthesis (codes+isss)

作者： Saidi, Selina Ernst, Rolf Uhrig, Sascha Theiling, Henrik de Dinechin, Benoit Dupont Tech Univ Carolo Wilhelmina Braunschweig Braunschweig Germany Airbus Grp Innovat Leiden Netherlands SYSGO AG Mainz Germany Kalray SA Montbonnot St Martin France

ISBN: (纸本)9781467383219

In real-time and safety-critical systems, the move towards multicores is becoming unavoidable in order to keep pace with the increasing required processing power and to meet the high integration trend while maintaining a reasonable power consumption. However, standard multicore systems are mainly designed to increase average performance, whereas embedded systems have additional requirements with respect to safety, reliability and realtime behavior. Therefore, the shift to multicores raises several challenges the embedded community has to face. These challenges involve the design of certifiable multicore platforms, the management of shared resources and the development/integration of parallel software. These issues are encountered at different steps of system development, from modeling and design to software implementation and hardware deployment. Therefore, both multicore/semiconductor manufacturers and the real-time community have to bridge the gap in order to meet the challenges imposed by multicores. The goal of this paper is to trigger such a discussion as an attempt to bridge the gap between the two worlds and to raise awareness about the hurdles and challenges that need to be tackled.

关键词： embedded systems parallel processing power aware computing resource allocation safety-critical software certifiable multicore platform design hardware deployment multicore systems parallel software development parallel software integration real-time system safety-critical system shared resource management software implementation system development Aerospace electronics hardware Multicore processing Real-time systems Safety software Timing safety-critical software real-time systems Embedded systems power aware computing software implementation avionics systems development computer software management of resources Computer hardware PARALLEL PROCESSING (COMPUTERS) Resource utilization Consumer safety safety software design

来源：评论

学校读者我要写书评

暂无评论

Computer Security by hardware-Intrinsic Authentication

Computer Security by Hardware-Intrinsic Authentication

引用

IEEE/ACM international conference on hardware/software codesign and system synthesis (codes+isss)

作者： Hoffman, Caio Cortes, Mario Aranha, Diego F. Araujo, Guido Univ Estadual Campinas Inst Comp Campinas SP Brazil

ISBN: (纸本)9781467383219

The widespread embedding of electronic devices into the daily-life objects, and their integration in the so called Internet of the Things ( IoT), has raised a number of challenges for the design of systems-on-Chip ( SoCs) devices. Tiny manufacturing costs, stringent security, and ultra-low power operation constraints have considerably raised SoC design requirements. More than incremental approaches which try to re-use current cryptographic mechanisms, the new generation of IoT devices will require novel solutions which deeply integrate their hardware-intrinsic features to program execution. This paper proposes a low-cost PUF-based authentication architecture aiming to secure code execution in IoT SoCs. The solution is deeply embedded into the processor micro-architecture, so as to minimize re-design costs and performance penalties. This new architecture model not only deals with the most common threats against code and data authenticity and integrity, but also provides an approach to extract from processor's caches a stable and unpredictable key that is used in the code and data authentication process.

关键词： Internet of Things authorisation cache storage computer architecture cryptography data integrity system-on-chip Internet of the things IoT SoC computer security cryptographic mechanisms daily-life objects data authentication process data authenticity electronic devices hardware-intrinsic authentication hardware-intrinsic features low-cost PUF-based authentication architecture processor caches processor microarchitecture systems-on-chip device design Authentication Computer architecture Cryptography Performance evaluation Random access memory software Computer Architecture Data Quality cryptography Computer Security system-on-chip Electron devices random access machine cache storage Internet of things Authentication Authorization Performance Evaluation computer software

来源：评论

学校读者我要写书评

暂无评论

Design methodologies for securing cyber-physical systems

Design methodologies for securing cyber-physical systems

引用

international conference on hardware/software codesign and system synthesis, codes+isss 2015

作者： Faruque, Mohammad Al Regazzoni, Francesco Pajic, Miroslav Dept. of Electrical Engineering and Computer Science University of California IrvineCA United States ALaRI Institute University of Lugano Lugano Switzerland Dept. of Electrical and Computer Engineering Duke University Durham NC United States

ISBN: (纸本)9781467383219

Cyber-Physical systems (CPS) are in most cases safety- and mission-critical. Standard design techniques used for securing embedded systems are not suitable for CPS due to the restricted computation and communication budget available in the latter. In addition, the sensitivity of sensed data and the presence of actuation components further increase the security requirements of CPS. To address these issues, it is necessary to provide new design methods in which security is considered from the beginning of the whole design flow and addressed in a holistic way. In this paper, we focus on the design of secure CPS as part of the complete CPS design process, and provide insights into new requirements on platform-aware design of control components, design methodologies and architectures posed by CPS design. We start by discussing methods for the multi-disciplinary modeling, simulation, tools, and software synthesis challenges for CPS. We also present a framework for design of secure control systems for CPS, while taking into account properties of the underlying computation and communication platforms. Finally, we describe the security challenges in the computing hardware that is used in CPS. © 2015 IEEE.

关键词： Cyber Physical system

来源：评论

学校读者我要写书评

暂无评论

Completeness Bounds and Sequentialization for Model Checking of Interacting Firmware and hardware

Completeness Bounds and Sequentialization for Model Checking...

引用

IEEE/ACM international conference on hardware/software codesign and system synthesis (codes+isss)

作者： Ahn, Sunha Malik, Sharad Gupta, Aarti Princeton Univ Princeton NJ 08544 USA

ISBN: (纸本)9781467383219

An emerging trend in system design is to implement complex system management functions in firmware ( FW). This changing design scenario requires support for verifying FW in the context of its hardware ( HW) environment. As shown in previous work, there is value in a unified HW-FW model for driving the verification tasks. This model can help identify specific commonly-occurring interaction patterns between the HW and FW. These patterns enable pruning the verification search space as demonstrated in previous work in automating FW test generation using concolic testing. In this work, we introduce a bounded model checking ( BMC)-based methodology for FW verification. Although BMC is effective for finding bugs by unrolling the underlying transition system up to some bound, it requires a completeness threshold on the bound to ensure complete verification. We show how commonly occurring FW code patterns can be exploited, using inexpensive static analysis techniques, to determine this completeness bound. Further, we show how this bound analysis, combined with the interaction patterns in the unified HW-FW model, is used to sequentialize the concurrent FW and HW code, i. e., to derive a sequential program that represents the parallel interaction of the FW and HW. This enables the direct application of standard software model checkers such as CBMC on this sequentialized program. We have automated this process by implementing: ( i) a static completeness bound analyzer on top of the tool Frama-C, and ( ii) a sequentializer to generate code for verification by the CBMC model checker. We evaluate the resulting tool using three real FW benchmarks, each consisting of a Linux device driver and its interacting QEMU-emulated HW code with multiple correctness properties. We successfully computed the BMC completeness bounds for 41 out of 46 properties and completed model checking for 12 out of 16 FW transactions.

关键词： Firmware

来源：评论

学校读者我要写书评

暂无评论

Power-awareness and smart-resource management in embedded computing systems

Power-awareness and smart-resource management in embedded co...

引用

IEEE/ACM international conference on hardware/software codesign and system synthesis (codes+isss)

作者： Santambrogio, M. D. Ayala, Jose L. Campanoni, Simone Cattaneo, R. Durelli, G. C. Ferroni, M. Nacci, A. Pagan, J. Zapater, M. Vallejo, M. Politecn Milan DEIB I-20133 Milan Italy Univ Complutense Madrid DACYA E-28040 Madrid Spain Northwestern Univ EELS Evanston IL USA UPM CCS Madrid Spain Univ Nacl Colombia Dept Elect Energy Automat Grp UNAL Bogota Colombia Politecn Milan Dipartimento Elettron Informaz & Bioingn Milan Italy Univ Complutense Madrid DACYA Ctr Computat Simulat E-28040 Madrid Spain Univ Nacl Colombia Dept Elect Energy Automat Grp UNAL Bogota Colombia

ISBN: (纸本)9781467383219

Resources such as quantities of transistors and memory, the level of integration and the speed of components have increased dramatically over the years. Even though the technologies have improved, we continue to apply outdated approaches to our use of these resources. Key computer science abstractions have not changed since the 1960's. Therefore this is the time for a fresh approach to the way systems are designed and used.

关键词： embedded systems power aware computing computer science abstraction embedded computing system power-awareness smart-resource management Accuracy Distortion Multicore processing Parallel processing Program processors Runtime Semantics power aware computing Program processors Embedded computing Runtime PARALLEL PROCESSING (COMPUTERS) Embedded systems Semantics abnormal shapes distortion semiotics

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共60页 << < 15 16 17 18 19 20 21 22 23 24 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：