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system-level memory optimization for high-level synthesis of component-based SoCs 14

System-level memory optimization for high-level synthesis of...

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2014 international conference on hardware/software codesign and system synthesis, codes+isss 2014

作者： Pilato, Christian Mantovani, Paolo Di Guglielmo, Giuseppe Carloni, Luca P. Department of Computer Science Columbia University New YorkNY United States

ISBN: (纸本)9781450330510

The design of specialized accelerators is essential to the success of many modern systems-on-Chip. Electronic system-level design methodologies and high-level synthesis tools are critical for the efficient design and optimization of an accelerator. Still, these methodologies and tools offer only limited support for the optimization of the memory structures, which are often responsible for most of the area occupied by an accelerator. To address these limitations, we present a novel methodology to automatically derive the memory subsystems of SoC accelerators. Our approach enables compositional design-space exploration and promotes design reuse of the accelerator specifications. We illustrate its effective-ness by presenting experimental results on the design of two accelerators for a high-performance embedded application. Copyright 2014 ACM.

关键词： system-on-chip

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Code Generation from a Domain-specific Language for C-based HLS of hardware Accelerators 14

Code Generation from a Domain-specific Language for C-based ...

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international conference on hardware / software codesign and system synthesis (codes+isss)

作者： Reiche, Oliver Schmid, Moritz Hannig, Frank Membarth, Richard Teich, Juergen Friedrich Alexander Univ Erlangen NUrnberg FAU Dept Comp Sci Erlangen Germany Saarland Univ Intel Visual Comp Inst Saarbrucken Germany

ISBN: (纸本)9781450330510

As today's computer architectures are becoming more and more heterogeneous, a plethora of options including CPUs, GPUs, DSPs, reconfigurable logic (FPGAs), and other application-specific processors come into consideration for close-to-sensor processing. Especially, in the domain of image processing on mobile devices, among numerous design challenges, a very stringent energy budget is of utmost importance, making embedded GPUs and FPGAs ideal targets for implementation. Recently, the HIPA(cc) framework was proposed as a means for automatic code generation of image processing algorithms for embedded GPUs, based on a Domain-Specific Language (DSL). Despite of huge advancements in High-Level synthesis (HLS) for FPGAs, designers are still required to have detailed knowledge about coding techniques and the targeted architecture to achieve efficient solutions. As a remedy, in this work, we propose code generation techniques for C-based HLS from a common high-level DSL description targeting FPGAs. Our approach includes FPGA-specific memory architectures for handling point and local operators, numerous high-level transformations, and automatic test bench generation. We evaluate our approach by comparing the resulting hardware accelerators to existing frameworks in terms of performance and resource requirements. Moreover, we assess the achieved energy efficiency in contrast to software implementations, generated by HIPAcc from the same code base, executed on GPUs.

关键词： Code generation domain specific language image processing high-level synthesis hardware accelerator FPCA CPU

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Automated Firmware Testing using Firmware-hardware Interaction Patterns 14

Automated Firmware Testing using Firmware-Hardware Interacti...

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international conference on hardware / software codesign and system synthesis (codes+isss)

作者： Ahn, Sunha Malik, Sharad Princeton Univ Princeton NJ 08544 USA

ISBN: (纸本)9781450330510

Firmware is low-level software which can directly access hardware and is often shipped with the hardware platform. This component of the system is increasing in scale and importance, and thus firmware validation is a critical part of system validation. Firmware validation relies on the interacting hardware components which are usually not available until the late design stages. This is generally addressed through co-simulating C/C++ based firmware code and HDL hardware models (including systemC). However, this tends to be slow, and is further exacerbated by the large number of possible interleavings between the concurrent firmware and hardware threads. Typically, in the co-simulation, the scheduler, such as the systemC scheduler, will only explore a single, or at best a small number of possible firmware-hardware interleavings and thus may miss critical bugs. In this paper we present an alternative approach to firmware validation that is based on automatically generating a test-set for the firmware with the goal of complete path coverage while considering its interactions with hardware and other firmware threads. It uses a service-function based Transaction Level Model (TLM) which has been used in the past for firmware hardware codesign. The test generation is based on concolic testing which has been used successfully in software test generation. However, existing concolic testing tools are used for test-generation of sequential code, and cannot directly consider the interaction of other hardware/firmware threads with the target firmware thread during test generation. We address this limitation by exploiting specific interaction patterns between the firmware and hardware threads that can be analyzed from the TLM. We show how these patterns, along with the firmware and hardware threads are used to automatically generate a sequential program that is test-equivalent to the target firmware transaction and that can be used with a standard sequential program concolic test

关键词： firmware hardware-software codesign multi-threading program testing program verification C++ based firmware code Frama-C HDL hardware models KLEE Linux device driver code QEMU emulated hardware code systemC scheduler TLM automated firmware testing concolic testing tools concurrent firmware firmware benchmarks firmware transaction firmware validation firmware-hardware codesign firmware-hardware interaction patterns firmware-hardware interleavings hardware components hardware-firmware thread interaction low-level software multithreaded interactions sequential code test-generation service-function based transaction level model software test generation standard sequential program concolic test generator static code analyzer system validation Benchmark testing Computer bugs Generators hardware Microprogramming software Firmware Computer hardware Trefoil Microprogramming Benchmark testing Multithreading Test generation hardware/software co-design program testing program verification dynamos LOW LEVEL computer software Transmission line measurements system validation

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system-of-PUFs: Multilevel Security for Embedded systems 14

System-of-PUFs: Multilevel Security for Embedded Systems

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international conference on hardware / software codesign and system synthesis (codes+isss)

作者： Konigsmark, S. T. Choden Hwang, Leslie K. Chen, Deming Wong, Martin D. F. Univ Illinois Dept Elect & Comp Engn Champaign IL 61820 USA

ISBN: (纸本)9781450330510

Embedded systems continue to provide the core for a wide range of applications, from smart-cards for mobile payment to smart-meters for power-grids. The resource and power dependency of embedded systems continues to be a challenge for state-of-the-art security practices. Moreover, even theoretically secure algorithms are often vulnerable in their implementation. With decreasing cost and complexity, physical attacks are an increasingly important threat. This threat led to the development of Physically Unclonable Functions (PUFs) which are disordered physical systems with various applications in hardware security. However, consistent security oriented design of embedded systems remains a challenge, as most formalizations and security models are concerned with isolated physical components or high-level concept. We provide four unique contributions: (i) We propose a system-level security model to overcome the chasm between secure components and requirements of high-level protocols;this enables synergy between component-oriented security formalizations and theoretically proven protocols. (ii) An analysis of current practices in PUF protocols using the proposed system-level security model;we identify significant issues and expose assumptions that require costly security techniques. (iii) A system-of-PUF (SoP) that utilizes the large PUF design-space to achieve security requirements with minimal resource utilization;SoP requires 64% less gate-equivalent units than recently published schemes. (iv) A multilevel authentication protocol based on SoP which is validated using our system-level security model and which overcomes current vulnerabilities. Furthermore, this protocol offers breach recognition and recovery.

关键词： Physically Unclonable Functions hardware Authentication

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Metronomy: A Function-Architecture Co-simulation Framework for Timing Verification of Cyber-Physical systems 14

Metronomy: A Function-Architecture Co-simulation Framework f...

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international conference on hardware / software codesign and system synthesis (codes+isss)

作者： Guo, Liangpeng Zhu, Qi Nuzzo, Pierluigi Passerone, Roberto Sangiovanni-Vincentelli, Alberto Lee, Edward A. Univ Calif Berkeley Berkeley CA 94720 USA Univ Calif Riverside Riverside CA 92521 USA Univ Trento Trento TN Italy

ISBN: (纸本)9781450330510

As the design complexity of cyber-physical systems continues to grow, modeling the system at higher abstraction levels with formal models of computation is increasingly appealing since it enables early design verification and analysis. One of the most important aspects in system modeling and analysis is timing. However, it is very challenging to analyze and verify timing at the early design stages, as the design representation is quite abstract and trade-offs have to be made between the performance requirements defined in terms of system functionality and the cost of the feasible architecture that can implement the functionality. In this paper, we present Metronomy, a function-architecture co-simulation framework that integrates functional modeling from Ptolemy and architectural modeling from the Metroll environment via a mapping interface. Metronomy exploits contract theory for timing verification and design space exploration via co-simulation. Two case studies on an electrical power system and a paper-feed sub-system for a high speed printing press demonstrate the effectiveness of our approach.

关键词： Cyber-Physical system Co-simulation Timing

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A Low Cost Acceleration Method for hardware Trojan Detection Based on Fan-out Cone Analysis 14

A Low Cost Acceleration Method for Hardware Trojan Detection...

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international conference on hardware / software codesign and system synthesis (codes+isss)

作者： Zhou, Bin Zhang, Wei Thambipillai, Srikanthan Teo, J. K. J. Nanyang Technol Univ Sch Comp Engn Singapore Singapore Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Peoples R China Harbin Inst Technol Res Ctr Basic Space Sci Harbin Heilongjiang Peoples R China

ISBN: (纸本)9781450330510

Fabless semiconductor industry and government agencies have raised serious concerns about tampering with inserting hardware Trojans in an integrated circuit supply chain in recent years. In this paper, a low hardware overhead acceleration method of the detection of HTs based on the insertion of 2-to-1 MUXs as test points is proposed. In the proposed method, the fact that one logical gate has a significant impact on the transition probability of the logical gates in its logical fan-out cone is utilized to optimize the number of the insertion MUXs. The nets which have smaller transition probability than the threshold value set by the user and minimal logical depth from the primary inputs are selected as the candidate nets. As for each candidate net, only its input net with smallest signal probability is required to be inserted the MUXs based test points until the minimal transition probability of the entire circuit is no smaller than the threshold value. Experiment results on ISCAS'89 benchmark circuits show that our proposed method can achieve remarkable improvement of transition probability with small overhead penalty.

关键词： hardware Trojan Fan-out cone Low cost Signal probability Transition probability

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Timing Analysis of Erroneous systems 14

Timing Analysis of Erroneous Systems

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international conference on hardware / software codesign and system synthesis (codes+isss)

作者： Assare, Omid Gupta, Rajesh Univ Calif San Diego Dept Comp Sci & Engn La Jolla CA 92093 USA

ISBN: (纸本)9781450330510

Erroneous systems allow timing errors to occur during execution, but use measures to ensure continued operation through changes in operating parameters (voltage and frequency), error correction at various levels of the system, or ensuring controlled occurrence of errors to perform approximate computing. In this paper, we are interested in characterization of error behavior at the level of instructions and programs. We propose Inter- and Intra-Program Variation as measures of error rate variability in different programs and among instructions of a program, respectively. We also characterize the error rate variation caused by the program input data and show that it is comparable to other sources of variability such as process variation. Finally, we present an analysis of the physical location of errors in hardware, identify regions in which most of the errors occur, and how different programs change the distribution of errors among these regions. In order to enable reliable timing analysis of large programs, we propose Clustered Timing Model (CTM), a high level timing model based on clustering functionally similar timing paths of the processor, and develop a CTM for LEON3, a representative in-order RISC processor. The accuracy of the model is verified using our variation-aware timing analysis framework with an average error of 3.9% (max. 6.7%) across a wide range of voltage-temperature corners.

关键词： erroneous systems variability process variation delay faults variation-aware timing analysis dynamic error estimation and software error behavior

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A PCM Translation Layer for Integrated Memory and Storage Management 14

A PCM Translation Layer for Integrated Memory and Storage Ma...

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international conference on hardware / software codesign and system synthesis (codes+isss)

作者： Chang, Bing-Jing Chang, Yuan-Hao Chang, Hung-Sheng Kuo, Tei-Wei Li, Hsiang-Pang Macronix Int Co Ltd Emerging Syst Lab Hsinchu Taiwan Natl Taiwan Univ Dept Comp Sci & Informat Engn Taipei Taiwan Acad Sinica Inst Informat Sci Taipei Taiwan Acad Sinica Res Ctr Informat Technol Innovat Taipei Taiwan

ISBN: (纸本)9781450330510

Phase change memory (PCM) is known for its potentials as main memory and as storage. In contrast to the past work, this work presents a PCM translation layer that considers how the main memory is used by the operating system together with the usage patterns of storage by trading their performance and reliability. In particular, a joint management scheme is proposed to improve the capability of PCM as both main memory and storage so as to enhance the performance of the entire system. The endurance issue of PCM for main memory is resolved by utilizing the potentially large capacity of the PCM storage space with limited modifications to the existing operating system implementations. Moreover, three commands are proposed to help operating system engineers to take advantage of PCM as main memory and storage by reducing I/O overheads and speeding up both the initialization and termination of program executions. The experimental results show that the performance of PCM as both main memory and storage can be significantly improved with reasonable lifetime, while the system overhead is very limited under coarse-grained wear leveling.

关键词： operating systems (computers) phase change memories program verification storage management I/O overheads PCM storage space PCM translation layer coarse-grained wear leveling integrated memory management integrated storage management joint management scheme operating system operating system implementations phase change memory program executions hardware Joints Memory management Operating systems Performance evaluation Phase change materials Random access memory Store management Operating systems Phase change memory main memory Pulse code modulation PROGRAM EXECUTION random access machine program verification Phase change materials Computer hardware Joints Joints Performance Evaluation

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Flattening-based Mapping of Imperfect Loop Nests for CGRAs 14

Flattening-based Mapping of Imperfect Loop Nests for CGRAs

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international conference on hardware / software codesign and system synthesis (codes+isss)

作者： Lee, Jongeun Seo, Seongseok Lee, Hongsik Sim, Hyeon Uk UNIST Sch ECE Ulsan South Korea

ISBN: (纸本)9781450330510

For loop accelerators such as coarse-grained reconfigurable architectures (CGRAs) and GP-GPUs, nested loops represent an important source of parallelism. Existing solutions to mapping nested loops on CGRAs, however, are either designed for perfectly nested loops only, or expensive and inflexible. Efficient CGRA mapping of imperfect loops with arbitrary nesting depth still remains a challenge. In this paper we propose a compiler-hardware co-operative approach that is flexible and yet able to generate efficient mappings for imperfect nested loops. It is based on loop flattening, but to mitigate the negative impact of flattening we combine loop fission and a light-weight architecture extension that is designed to accelerate common operation patterns appearing frequently in flattened loops. Our experimental results using imperfect loops from multimedia and DSP domains demonstrate that our special operations can cover a large portion of nested loop operations, improve performance of nested loops by nearly 30% over using loop flattening only, and achieve near-ideal executions on CGRAs for imperfect loops.

关键词： parallel processing program compilers program control structures CGRA DSP domains GP-GPUs coarse-grained reconfigurable architectures compiler-hardware cooperative approach flattening-based loop nest mapping light-weight architecture extension loop accelerators loop fission loop flattening multimedia domains nested loop mapping parallelism source Arrays Kernel Nickel Pipeline processing Registers Coarse-grained Reconfigurable Architecture Loops program control structures Imperfect Pipeline processing compilers Registers PARALLEL PROCESSING (COMPUTERS) Nickel Contraceptive Coil FLATTENING Kernel MAPPING(MATHEMATICAL)

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Towards Scalable Symbolic Routing for Multi-Objective Networked Embedded system Design and Optimization 14

Towards Scalable Symbolic Routing for Multi-Objective Networ...

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international conference on hardware / software codesign and system synthesis (codes+isss)

作者： Graf, Sebastian Reimann, Felix Glass, Michael Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Erlangen Germany

ISBN: (纸本)9781450330510

Symbolic encoding for resource allocation, task binding, and message routing during multi-objective design space exploration (DSE) has gained significant attention in recent years. To determine the message routing, existing symbolic approaches typically rely on an explicit encoding of routing hops which results in a huge number of required variables and/or constraints. As a result, these approaches fail in case of large network diameters and/or a huge number of messages or resources and even for smaller problems, the convergence of the involved optimization process suffers. To tackle this shortcomings, this work proposes three novel symbolic routing encoding strategies that all avoid to encode hops explicitly, but are based on an encoding of individual links or complete sender-receiver paths, but still cover the same design space. The result is a more compact problem representation with less constraints and, in particular, less variables;the latter eliminates ineffective degrees of freedom from the search space and significantly enhances the optimization quality of a multi-objective optimization with even non-linear objectives. In an extensive test-suite, three major classes of wired networked embedded systems are considered: (a) hierarchical stars as in MPSoCs or automotive, (b) redundant backbone buses as common in rail systems or avionics, and (c) mesh-based architectures that often occur in NoC-based MPSoCs. For all three classes, the proposed approaches significantly outperform existing techniques in both scalability and optimization quality and, thus, considerably enlarge the field of application of a multi-objective DSE for the networked embedded system design.

关键词： Embedded systems Encoding Optimization Receivers Resource management Routing Scalability Network routing Scalability Embedded systems embedded system design management of resources Receivers coding

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