检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

566 篇 会议
27 篇 期刊文献

馆藏范围

593 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

291 篇 工学
- 284 篇 计算机科学与技术...
- 248 篇 软件工程
- 66 篇 电子科学与技术（可...
- 30 篇 电气工程
- 29 篇 信息与通信工程
- 26 篇 控制科学与工程
- 8 篇 动力工程及工程热...
- 4 篇 机械工程
- 4 篇 光学工程
- 4 篇 材料科学与工程（可...
- 4 篇 建筑学
- 4 篇 土木工程
- 3 篇 安全科学与工程
- 2 篇 力学（可授工学、理...
- 2 篇 仪器科学与技术
- 1 篇 化学工程与技术
- 1 篇 纺织科学与工程
- 1 篇 轻工技术与工程
- 1 篇 航空宇航科学与技...
71 篇 理学
- 48 篇 数学
- 33 篇 系统科学
- 7 篇 统计学（可授理学、...
- 4 篇 物理学
- 1 篇 生物学
43 篇 管理学
- 35 篇 管理科学与工程(可...
- 13 篇 工商管理
- 10 篇 图书情报与档案管...
4 篇 法学
- 3 篇 社会学
- 1 篇 法学
3 篇 经济学
- 3 篇 应用经济学

主题

122 篇 hardware
73 篇 computer archite...
54 篇 embedded system
50 篇 permission
40 篇 application soft...
38 篇 system-on-a-chip
37 篇 embedded systems
35 篇 energy consumpti...
33 篇 algorithm design...
31 篇 computational mo...
28 篇 space exploratio...
28 篇 software
27 篇 field programmab...
24 篇 runtime
23 篇 system-on-chip
22 篇 timing
22 篇 costs
20 篇 delay
19 篇 registers
19 篇 high level synth...

机构

8 篇 center for embed...
6 篇 school of comput...
6 篇 department of co...
5 篇 school of inform...
5 篇 center for embed...
5 篇 institute for in...
4 篇 university of er...
4 篇 department of el...
4 篇 univ elect sci &...
4 篇 nec laboratories...
4 篇 philips research...
3 篇 integrated signa...
3 篇 department of el...
3 篇 department of co...
3 篇 chongqing univ c...
3 篇 philips research...
3 篇 graz university ...
3 篇 arizona state un...
3 篇 univ calif river...
3 篇 politecn torino ...

作者

7 篇 sri parameswaran
7 篇 ogras umit y.
7 篇 parameswaran sri
7 篇 nikil dutt
7 篇 leupers rainer
6 篇 dutt nikil
6 篇 mitra tulika
5 篇 jiang wei
5 篇 pasricha sudeep
5 篇 rolf ernst
5 篇 robert p. dick
5 篇 jinyu zhan
5 篇 gerstlauer andre...
5 篇 tei-wei kuo
5 篇 wei jiang
5 篇 yuan-hao chang
5 篇 rainer leupers
5 篇 zhan jinyu
5 篇 fummi franco
4 篇 takach andres

语言

593 篇 英文

检索条件"任意字段=2014 International Conference on Hardware/Software Codesign and System Synthesis, CODES ISSS 2014"

共 593 条记录，以下是221-230 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Dark Silicon as a Challenge for hardware/software Co-Design

Dark Silicon as a Challenge for Hardware/Software Co-Design

引用

international conference on hardware / software codesign and system synthesis (codes+isss)

作者： Shafique, Muhammad Garg, Siddharth Mitra, Tulika Parameswaran, Sri Henkel, Joerg Karlsruhe Inst Technol CES Karlsruhe Germany Univ Waterloo Dept ECE Waterloo ON Canada Natl Univ Singapore Sch Comp Singapore Singapore Univ New South Wales Sch Comp Sci & Engn Sydney NSW Australia

ISBN: (纸本)9781450330510

Dark Silicon refers to the observation that in future technology nodes, it may only be possible to power-on a fraction of on-chip resources (processing cores, hardware accelerators, cache blocks and so on) in order to stay within the power budget and safe thermal limits, while the other resources will have to be kept powered-off or "dark". In other words, chips will have an abundance of transistors, i.e., more than the number that can be simultaneously powered-on. Heterogeneous computing has been proposed as one way to effectively leverage this abundance of transistors in order to increase performance, energy efficiency and even reliability within power and thermal constraints. However, several critical challenges remain to be addressed including design, automated synthesis, design space exploration and run-time management of heterogeneous dark silicon processors. The hardware/software co-design and synthesis community has potentially much to contribute in solving these new challenges introduced by dark silicon and, in particular, heterogeneous computing. In this paper, we identify and highlight some of these critical challenges, and outline some of our early research efforts in addressing them.

关键词： hardware-software codesign power aware computing automated synthesis design space exploration energy efficiency improvement hardware-software co-design heterogeneous computing heterogeneous dark silicon processors on-chip resources performance improvement power budget power constraint reliability improvement run-time management safe thermal limits thermal constraint transistors Computer architecture hardware Program processors Reliability Silicon Switches hardware/software co-design power budget power aware computing Transistor Device Component Program processors Computer Architecture Silicon Switches performance boost Computer hardware Co-design Space Exploration

来源：评论

学校读者我要写书评

暂无评论

An Efficient Technique for Computing Importance Measures in Automatic Design of Dependable Embedded systems 14

An Efficient Technique for Computing Importance Measures in ...

引用

international conference on hardware / software codesign and system synthesis (codes+isss)

作者： Aliee, Hananeh Glass, Michael Khosravi, Faramarz Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Erlangen Germany

ISBN: (纸本)9781450330510

Importance measure analysis judges the relative importance of components in a system and reveals how each component contributes to the system reliability. In the design of large and complex systems, importance measure analysis can therefore be employed to guide an optimization tool which design decisions to investigate to gain higher reliability. While previous research has mainly concentrated on developing analytical importance measure techniques, the automatic and frequent computing of importance measures as required in the context of design space exploration has got very few, if any attention. This paper presents a highly efficient technique to compute the reliability and structural importance measures of components of a system. The proposed technique considers the reliability of a system implementation and subsequently analyzes the importance measures of its components based on a state-of-the-art Monte Carlo simulation. The technique can therefore estimate the importance measures of all components concurrently, highly improving the performance of the computation compared, e.g., to the well-known Birnbaum approach by the factor of 2n with n being the number of components. Moreover, we show how this algorithm can be extended to support importance measure analysis in the existence of transient faults which is essential since in future systems, transient faults are expected to cause relatively more failures than permanent faults. We integrated the proposed analysis approach in an existing multi-objective local-search algorithm that is part of an automatic system-level design space exploration which seeks for system implementations with highest reliability at lowest possible cost. Experimental results show that the proposed algorithm performs efficiently with negligible imprecision, even for large real world examples.

关键词： importance sampling search problems Birnbaum approach Monte Carlo simulation automatic design automatic system-level design space exploration complex system dependable embedded systems importance measure analysis importance measure techniques large system multiobjective local-search algorithm optimization tool permanent fault structural importance measures system implementation system reliability transient fault Algorithm design and analysis Boolean functions hardware Reliability engineering Space exploration Transient analysis Computer-Aided Design transient fault system implementation permanent fault Space Exploration Algorithm design and analysis Reliability engineering tabu search Complex systems Transient analysis Boolean functions importance sampling Monte Carlo technique Computer hardware

来源：评论

学校读者我要写书评

暂无评论

HYPNOS: An Ultra-Low Power Sleep Mode with SRAM Data Retention for Embedded Microcontrollers 14

HYPNOS: An Ultra-Low Power Sleep Mode with SRAM Data Retenti...

引用

international conference on hardware / software codesign and system synthesis (codes+isss)

作者： Jayakumar, Hrishikesh Raha, Arnab Raghunathan, Vijay Purdue Univ W Lafayette IN 47907 USA

ISBN: (纸本)9781450330510

In heavily duty-cycled embedded systems, the energy consumed by the microcontroller in idle mode is often the bottleneck for battery lifetime. Existing solutions address this problem by placing the microcontroller in a low power (sleep) state when idle, and preserving application state either by retaining the data in-situ in SRAM, or by checkpointing it to FLASH. However, both these approaches have notable drawbacks. In-situ data retention requires the SRAM to remain powered in sleep mode, while checkpointing to FLASH involves significant energy and time overheads. This paper proposes a new ultra-low power sleep mode for micro controllers that overcomes the limitations of both these approaches. Our technique, HYPNOS, is based on the key observation that the on-chip SRAM in a microcontroller exhibits 100% data retention even at a much lower supply voltage (as much as 10x lower) than the typical operating voltage of the microcontroller. HYPNOS exploits this observation by performing extreme voltage scaling when the microcontroller is in sleep mode. We implement and evaluate HYPNOS for the TI MSP430G2452 microcontroller and show that the MCU draws only 26nA in the proposed sleep mode, which is 4x lower than any existing sleep mode that preserves SRAM contents. Further, we show that a complete wireless sensing system using HYPNOS only depletes battery capacity by 42.6nAh in an hour. By decreasing the average power consumption to such minuscule levels, HYPNOS takes a significant step forward in making perpetual systems a reality through the use of energy harvesting.

关键词： SRAM chips checkpointing embedded systems microcontrollers power aware computing power consumption storage management Flash HYPNOS MCU SRAM content preservation SRAM data retention TI MSP430G2452 microcontroller battery capacity battery lifetime embedded microcontrollers energy consumption energy harvesting energy overhead extreme voltage scaling heavily duty-cycled embedded system microcontroller operating voltage onchip SRAM time overhead ultralow power sleep mode wireless sensing system Microcontrollers Phasor measurement units Power demand Registers SRAM cells Switches Microcontrollers checkpointing sleeping mode Static random access storage Power consumption Battery Life power aware computing Battery Capacity Flashing Phasor measurement units Store management Power demand Registers energy harvesting Embedded systems

来源：评论

学校读者我要写书评

暂无评论

Dark silicon as a challenge for hardware/software co-design

Dark silicon as a challenge for hardware/software co-design

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Muhammad Shafique Siddharth Garg Tulika Mitra Sri Parameswaran Jörg Henkel Chair for Embedded Systems (CES) Karlsruhe Institute of Technology Germany Department of ECE University of Waterloo Canada University of New South Wales Sydney NSW AU

Dark Silicon refers to the observation that in future technology nodes, it may only be possible to power-on a fraction of on-chip resources (processing cores, hardware accelerators, cache blocks and so on) in order to stay within the power budget and safe thermal limits, while the other resources will have to be kept powered-off or “dark”. In other words, chips will have an abundance of transistors, i.e., more than the number that can be simultaneously powered-on. Heterogeneous computing has been proposed as one way to effectively leverage this abundance of transistors in order to increase performance, energy efficiency and even reliability within power and thermal constraints. However, several critical challenges remain to be addressed including design, automated synthesis, design space exploration and run-time management of heterogeneous dark silicon processors. The hardware/software co-design and synthesis community has potentially much to contribute in solving these new challenges introduced by dark silicon and, in particular, heterogeneous computing. In this paper, we identify and highlight some of these critical challenges, and outline some of our early research efforts in addressing them.

关键词： Silicon Program processors Reliability Computer architecture Switches hardware

来源：评论

学校读者我要写书评

暂无评论

Embedded systems Week 2011, ESWEEK 2011 - Proceedings of the 9th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, codes+isss'11

Embedded Systems Week 2011, ESWEEK 2011 - Proceedings of the...

引用

Embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/ACM international conference on hardware/software-codesign and system synthesis, codes+isss'11

ISBN: (纸本)9781450307154

The proceedings contain 41 papers. The topics discussed include: memory controllers for high-performance and real-time MPSoCs: requirements, architectures, and future trends;an energy-efficient patchable accelerator for post-silicon engineering changes;a bursty multi-port memory controller with quality-of-service guarantees;SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs;a design methodology to implement memory accesses in high-level synthesis;design and architectures for dependable embedded systems;SPMVisor: dynamic scratchpad memory virtualization for secure, low power, and high performance distributed on-chip memories;dynamic, multi-core cache coherence architecture for power-sensitive mobile processors;PRET DRAM controller: bank privatization for predictability and temporal isolation;and DistRM: distributed resource management for on-chip many-core systems.

关键词：

来源：评论

学校读者我要写书评

暂无评论

hardware neural network accelerators

Hardware neural network accelerators

引用

11th ACM/IEEE international conference on hardware/software codesign and system synthesis, codes+isss 2013

作者： Temam, O. INRIA Saclay France

""Because of increasingly stringent energy constraints (e.g., Dark Silicon, there is a growing consensus in the community that we may be moving towards heterogeneous multi-core architectures, composed of a m... 详细信息

ISBN: (纸本)9781479914173

关键词： application specific integrated circuits fault tolerant computing graphics processing units learning (artificial intelligence) multiprocessing systems neural nets parallel architectures power aware computing

来源：评论

学校读者我要写书评

暂无评论

system level synthesis of hardware for DSP applications using pre-characterized function implementations

System level synthesis of hardware for DSP applications usin...

引用

11th ACM/IEEE international conference on hardware/software codesign and system synthesis, codes+isss 2013

作者： Li, Shuo Farahini, Nasim Hemani, Ahmed Rosvall, Kathrin Sander, Ingo ES/ICT/KTH Forum 120 SE-164 40 Kista Sweden

ISBN: (纸本)9781479914173

SYLVA is a system level synthesis framework that transforms DSP sub-systems modeled as synchronous data flow into hardware implementations in ASIC, FPGAs or CGRAs. SYLVA synthesizes in terms of pre-characterized function implementations (FTMPs). It explores the design space in three dimensions, number of FTMPs, type of FTMPs and pipeline parallelism between the producing and consuming FTMPs. We introduce timing and interface model of FTMPs to enable reuse and automatic generation of Global Interconnect and Control (GLIC) to glue the FTMPs together into a working system. SYLVA has been evaluated by applying it to five realistic DSP applications and results analyzed for design space exploration, efficacy in generating GLIC by comparing to manually generated GLIC and accuracy of design space exploration by comparing the area and energy costs considered during the design space exploration based on pre-characterized FIMPs and the final results. © 2013 IEEE.

关键词： Data transfer

来源：评论

学校读者我要写书评

暂无评论

Bound-oriented parallel pruning approaches for efficient resource constrained scheduling of high-level synthesis

Bound-oriented parallel pruning approaches for efficient res...

引用

11th ACM/IEEE international conference on hardware/software codesign and system synthesis, codes+isss 2013

作者： Chen, Mingsong Zhou, Lei Pu, Geguang He, Jifeng Shanghai Key Laboratory of Trustworthy Computing East China Normal Univeristy China

ISBN: (纸本)9781479914173

As a key step of high-level synthesis (HLS), resource constrained scheduling (RCS) tries to find an optimal schedule which can dispatch all the operations with minimum latency under specific resource constraints. Branch-and-bound heuristics are promising to achieve such an optimal schedule quickly, since they can prune away large parts of infeasible solution space during the exploration. However, few of them are based on the prevalent multi-core platforms. Based on the bound information, this paper exploits the parallel pruning potentials from different perspectives and proposes various efficient techniques that can substantially reduce the overall RCS search efforts. The experimental results demonstrate that our approach can reduce the RCS time drastically. © 2013 IEEE.

关键词： High level synthesis

来源：评论

学校读者我要写书评

暂无评论

Automatic refinement of requirements for verification throughout the SoC design flow

Automatic refinement of requirements for verification throug...

引用

11th ACM/IEEE international conference on hardware/software codesign and system synthesis, codes+isss 2013

作者： Pierre, Laurence Bel Hadj Amor, Zeineb TIMA Laboratory CNRS-INPG-UJF 46 Avenue Félix Viallet 38031 Grenoble cedex France

ISBN: (纸本)9781479914173

This paper focuses on the verification of requirements for hardware/software systems on chip (SoC's) along the design flow. In the early stages of this flow, the Electronic system Level (ESL) description style, and languages such as systemC TLM, enable high-level debugging of the SoC functionality. In the last stages, hardware blocks become RTL or gate level (VHDL or Verilog) descriptions. We have developed two autonomous Assertion-Based Verification (ABV) solutions, for systemC TLM platforms and for VHDL/Verilog IP blocks: designs are automatically instrumented with ad hoc property checkers produced from requirements formalized as PSL assertions. Furthermore, for a comprehensive and seamless verification flow, analogous requirements should be verifiable before and after ESL-to-RTL hardware refinement. This requires the transformation of ESL assertions into their counterparts at the RT level. This paper discusses this issue and proposes a first set of transformation rules for the automatic refinement of PSL assertions from the system level to the signal level. Properties of an industrial case study are used as illustrative examples. © 2013 IEEE.

关键词： system-on-chip

来源：评论

学校读者我要写书评

暂无评论

synthesis-friendly techniques for tightly-coupled integration of hardware accelerators into shared-memory multi-core clusters

Synthesis-friendly techniques for tightly-coupled integratio...

引用

11th ACM/IEEE international conference on hardware/software codesign and system synthesis, codes+isss 2013

作者： Conti, Francesco Marongiu, Andrea Benini, Luca DEI Università di Bologna Italy

ISBN: (纸本)9781479914173

Several many-core designs tackle scalability issues by leveraging tightly-coupled clusters as building blocks, where low-latency, high-bandwidth interconnection between a small/medium number of cores and L1 memory achieves high performance/watt. Tight coupling of hardware accelerators into these multicore clusters constitutes a promising approach to further improve performance/area/watt. However, accelerators are often clocked at a lower frequency than processor clusters for energy efficiency reasons. In this paper, we propose a technique to integrate shared-memory accelerators within the tightly-coupled clusters of the STMicroelectronics STHORM architecture. Our methodology significantly relaxes timing constraints for tightly-coupled accelerators, while optimizing data bandwidth. In addition, our technique allows to operate the accelerator at an integer submultiple of the cluster frequency. Experimental results show that the proposed approach allows to recover up to 84% of the slow-down implied by reduced accelerator speed. © 2013 IEEE.

关键词： Energy efficiency

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共60页 << < 19 20 21 22 23 24 25 26 27 28 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：