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hardware neural network accelerators 13

Hardware neural network accelerators

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： O. Temam INRIA Saclay France

ISBN: (纸本)9781479914173

Because of increasingly stringent energy constraints (e.g., Dark Silicon, there is a growing consensus in the community that we may be moving towards heterogeneous multi-core architectures, composed of a mix of cores and accelerators. Because our community is traditionally focused on general-purpose computing, we have been especially considering accelerator approaches such as GPUs and reconfigurable circuits. An attractive alternative is to investigate accelerators which are focused on a few key algorithms: key algorithms still mean broad application scope, but few algorithms enable energy efficient and cost-effective accelerators.

关键词： Artificial neural networks hardware Computer architecture Circuit faults Biological neural networks Communities

来源：评论

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WHISK: An uncore architecture for Dynamic Information Flow Tracking in heterogeneous embedded SoCs 13

WHISK: An uncore architecture for Dynamic Information Flow T...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Joël Porquet Simha Sethumadhavan Department of Computer Science Columbia University NY

ISBN: (纸本)9781479914173

In this paper, we describe for the first time, how Dynamic Information Flow Tracking (DIFT) can be implemented for heterogeneous designs that contain one or more on-chip accelerators attached to a network-on-chip. We observe that implementing DIFT for such systems requires holistic platform level view, i.e., designing individual components in the heterogeneous system to be capable of supporting DIFT is necessary but not sufficient to correctly implement full-system DIFT. Based on this observation we present a new system architecture for implementing DIFT, and also describe wrappers that provide DIFT functionality for third-party IP components. Results show that our implementation minimally impacts performance of programs that do not utilize DIFT, and the price of security is constant for modest amounts of tagging and then sub-linearly increases with the amount of tagging.

关键词： Tagging system-on-chip Computer architecture Security hardware software Engines

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system level synthesis of hardware for DSP applications using pre-characterized function implementations 13

System level synthesis of hardware for DSP applications usin...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Shuo Li Nasim Farahini Ahmed Hemani Kathrin Rosvall Ingo Sander Royal Institute of Technology (KTH) Kista Sweden

ISBN: (纸本)9781479914173

SYLVA is a system level synthesis framework that transforms DSP sub-systems modeled as synchronous data flow into hardware implementations in ASIC, FPGAs or CGRAs. SYLVA synthesizes in terms of pre-characterized function implementations (FTMPs). It explores the design space in three dimensions, number of FTMPs, type of FTMPs and pipeline parallelism between the producing and consuming FTMPs. We introduce timing and interface model of FTMPs to enable reuse and automatic generation of Global Interconnect and Control (GLIC) to glue the FTMPs together into a working system. SYLVA has been evaluated by applying it to five realistic DSP applications and results analyzed for design space exploration, efficacy in generating GLIC by comparing to manually generated GLIC and accuracy of design space exploration by comparing the area and energy costs considered during the design space exploration based on pre-characterized FIMPs and the final results.

关键词： Libraries Abstracts Field programmable gate arrays

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Bound-oriented parallel pruning approaches for efficient resource constrained scheduling of high-level synthesis 13

Bound-oriented parallel pruning approaches for efficient res...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Mingsong Chen Lei Zhou Geguang Pu Jifeng He Shanghai Key Laboratory of Trustworthy Computing East China Normal Univeristy Shanghai China

ISBN: (纸本)9781479914173

As a key step of high-level synthesis (HLS), resource constrained scheduling (RCS) tries to find an optimal schedule which can dispatch all the operations with minimum latency under specific resource constraints. Branch-and-bound heuristics are promising to achieve such an optimal schedule quickly, since they can prune away large parts of infeasible solution space during the exploration. However, few of them are based on the prevalent multi-core platforms. Based on the bound information, this paper exploits the parallel pruning potentials from different perspectives and proposes various efficient techniques that can substantially reduce the overall RCS search efforts. The experimental results demonstrate that our approach can reduce the RCS time drastically.

关键词： Optimal scheduling Schedules Estimation Job shop scheduling Processor scheduling Delays

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Bio-inspired ultra lower-power neuromorphic computing engine for embedded systems 13

Bio-inspired ultra lower-power neuromorphic computing engine...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Beiye Liu Miao Hu Hai Li Yiran Chen Chun Xue Electrical & Computer Engineering Department University of Pittsburgh Pittsburgh USA Department of Computer Science City University of Hong Kong Hong Kong China

ISBN: (纸本)9781479914173

Neuromorphic computing, which is inspired by the working mechanism of human brain, recently emerges as a hot research area to combat the contradiction between the limited functions of computing systems and the ever increasing variety of applications. In this work, we will introduce our research on a bio-inspired neuromorphic embedded computing engine named Centaur, which aims to achieve an ultra-high power efficiency beyond One-TeraFlops-Per-Watt by adopting the bio-inspired computation model and the advanced memristor technology. The success of Centaur design may promote the embedded system power efficiency three orders of magnitude from the current level while the small footprint and real-time re-configurability of the design allow an easy integration into MPSoCs, enabling many emerging mobile and embedded applications.

关键词： Neuromorphics Memristors Engines Embedded systems hardware Training Computational efficiency

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Automatic refinement of requirements for verification throughout the SoC design flow 13

Automatic refinement of requirements for verification throug...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Laurence Pierre Zeineb Bel Hadj Amor TIMA Laboratory (CNRS-INPG-UJF) Grenoble cedex France

ISBN: (纸本)9781479914173

This paper focuses on the verification of requirements for hardware/software systems on chip (SoC's) along the design flow. In the early stages of this flow, the Electronic system Level (ESL) description style, and languages such as systemC TLM, enable high-level debugging of the SoC functionality. In the last stages, hardware blocks become RTL or gate level (VHDL or Verilog) descriptions. We have developed two autonomous Assertion-Based Verification (ABV) solutions, for systemC TLM platforms and for VHDL/Verilog IP blocks: designs are automatically instrumented with ad hoc property checkers produced from requirements formalized as PSL assertions. Furthermore, for a comprehensive and seamless verification flow, analogous requirements should be verifiable before and after ESL-to-RTL hardware refinement. This requires the transformation of ESL assertions into their counterparts at the RT level. This paper discusses this issue and proposes a first set of transformation rules for the automatic refinement of PSL assertions from the system level to the signal level. Properties of an industrial case study are used as illustrative examples.

关键词： system-on-chip hardware Program processors Registers Synchronization Time-varying systems Time-domain analysis

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A DRAM-flash index for native flash file systems 13

A DRAM-flash index for native flash file systems

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Chien-Chung Ho Po-Chun Huang Yuan-Hao Chang Tei-Wei Kuo Department of Computer Science and Information Engineering National Taiwan University Academia Sinica Institute of Information Science College of Information and Communication Engineering Sungkyunkwan University

ISBN: (纸本)9781479914173

Index structures are widely used in file systems and database applications for efficient data management. This paper exploits the respective characteristics of DRAM and flash memory for tree index designs, for which a native file system is taken as an example target in the research. Different from DRAM caching or buffering of flash-memory access in the past work, a hybrid index design that resides over DRAM and flash memory simulaneously is proposed to improve system performance and space management. Tree nodes migrate between DRAM and flash memory, as needed, in response to user access pattern so as to optimize the performance and to reduce managing overhead. The capability of the proposed design is evaluated by a series of experiments, for which we have very encouraging results.

关键词： flash memory index structure native flash file system overflow tree

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synthesis-friendly techniques for tightly-coupled integration of hardware accelerators into shared-memory multi-core clusters 13

Synthesis-friendly techniques for tightly-coupled integratio...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Francesco Conti Andrea Marongiu Luca Benini DEI - Università di Bologna

ISBN: (纸本)9781479914173

Several many-core designs tackle scalability issues by leveraging tightly-coupled clusters as building blocks, where low-latency, high-bandwidth interconnection between a small/medium number of cores and L1 memory achieves high performance/watt. Tight coupling of hardware accelerators into these multicore clusters constitutes a promising approach to further improve performance/area/watt. However, accelerators are often clocked at a lower frequency than processor clusters for energy efficiency reasons. In this paper, we propose a technique to integrate shared-memory accelerators within the tightly-coupled clusters of the STMicroelectronics STHORM architecture. Our methodology significantly relaxes timing constraints for tightly-coupled accelerators, while optimizing data bandwidth. In addition, our technique allows to operate the accelerator at an integer submultiple of the cluster frequency. Experimental results show that the proposed approach allows to recover up to 84% of the slow-down implied by reduced accelerator speed.

关键词： hardware Computer architecture Registers Clocks Ports (Computers) Couplings Bandwidth

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A cyber-physical system approach to artificial pancreas design 13

A cyber-physical system approach to artificial pancreas desi...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Mahboobeh Ghorbani Paul Bogdan University of Southern California Los Angeles CA USA

ISBN: (纸本)9781479914173

Healthcare costs in the US are among the highest in the world. Widespread chronic diseases such as diabetes constitute a significant cause of rising healthcare costs. Despite the increased need for smart healthcare systems that monitor patients' body balance, there is no coherent theory that facilitates the design and optimization of efficient and robust cyber physical systems. In this paper, we propose a mathematical model for capturing the dynamics of blood glucose characteristics (e.g., time dependent fractal behavior) observed in real world measurements via fractional calculus concepts. Building on our time dependent fractal model, we propose a novel mathematical model as well as hardware architecture for an artificial pancreas that relies on solving a constrained multi-fractal optimal control problem for regulating insulin injection. We verify the accuracy of our mathematical model by comparing it to conventional nonfractal models using real world measurements and showing that the nonlinear optimal controller based on fractal calculus concepts is superior to nonfractal controllers. We also verified the feasibility of in silico realization of the proposed optimal control algorithm by prototyping on FPGA platform.

关键词： Sugar Blood Insulin Fractals Mathematical model Heuristic algorithms Optimal control

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Scalable NoC-based architecture of neural coding for new efficient associative memories 13

Scalable NoC-based architecture of neural coding for new eff...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Jean-Philippe Diguet Marius Strum Nicolas Le Griguer Lydie Caetano Martha Johanna Sepúlveda CNRS Lab-STICC Lorient France Microelectronics Lab.-EPUSP Univ. of São Paulo Brazil UMR6285 Lab-STICC Lorient France

ISBN: (纸本)9781479914173

We present the first NoC-based hardware implementation of Neural Coding (NC), which is a new approach that opens outstanding perspectives for the design of associative memories and learning machines. We first propose optimized architectures of memories and processing elements that allow for an efficient distributed implementation. Then we introduce different NoC architectures to interconnect all elements, it provides the required scalability and takes advantage of parallel transfer opportunities. Performance, cost and energy consumption tradeoffs of various NoC solutions are compared and discussed. Based on previous implementation results, we run systemC-TLM that validate the behavior of the algorithm and of the efficiency of the dedicated architecture. This work demonstrates that this architecture can meet expected requirements in terms of scalability and hierarchy, and consequently that NC-based architectures are compliant with efficient hardware implementations of a new and promising model of associative memories.

关键词： Neurons Encoding Associative memory Computer architecture hardware Vectors Neural networks

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