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Embedded supercomputing in FPGAs with the VectorBlox MXP Matrix Processor 13

Embedded supercomputing in FPGAs with the VectorBlox MXP Mat...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Aaron Severance Guy G.F. Lemieux VectorBlox Computing Inc. University of British Columbia

ISBN: (纸本)9781479914173

Embedded systems frequently use FPGAs to perform highly parallel data processing tasks. However, building such a system usually requires specialized hardware design skills with VHDL or Verilog. Instead, this paper presents the VectorBlox MXP Matrix Processor, an FPGA-based soft processor capable of highly parallel execution. Programmed entirely in C, the MXP is capable of executing data-parallel software algorithms at hardware-like speeds. For example, the MXP running at 200MHz or higher can implement a multi-tap FIR filter and output 1 element per clock cycle. MXP's parameterized design lets the user specify the amount of parallelism required, ranging from 1 to 128 or more parallel ALUs. Key features of the MXP include a parallel-access scratchpad memory to hold vector data and high-throughput DMA and scatter/gather engines. To provide extreme performance, the processor is expandable with custom vector instructions and custom DMA filters. Finally, the MXP seamlessly ties into existing Altera and Xilinx development flows, simplifying system creation and deployment.

关键词： Vectors Engines Field programmable gate arrays hardware Registers Finite impulse response filters Clocks

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CMSM: An efficient and effective Code Management for software Managed Multicores 13

CMSM: An efficient and effective Code Management for Softwar...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Ke Bai Jing Lu Aviral Shrivastava Bryce Holton Compiler Microarchitecture Laboratory Arizona State University Tempe Arizona USA

ISBN: (纸本)9781479914173

As we scale the number of cores in a multicore processor, scaling the memory hierarchy is a major challenge. software Managed Multicore (SMM) architectures are one of the promising solutions. In an SMM architecture, there are no caches, and each core has only a local scratchpad memory. If all the code and data of the task mapped to a core do not fit on its local scratchpad memory, then explicit code and data management is required. In this paper, we solve the problem of efficiently managing code on an SMM architecture. We extend the state of the art by: i) correctly calculating the code management overhead, ii) even in the presence of branches in the task, and iii) developing a heuristic CMSM (Code Mapping for software Managed multicores) that results in efficient code management execution on the local scratchpad memory. Our experimental results collected after executing applications from MiBench suite [1] on the Cell SPEs (Cell is an SMM architecture) [2], demonstrate that correct management cost calculation and branch consideration can improve performance by 12%. Our heuristic CMSM can reduce runtime in more than 80% of the cases, and by up to 20% on our set of benchmarks.

关键词： Memory management Multicore processing Interference Switches software Estimation

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Instruction set extensions for Dynamic Time Warping 13

Instruction set extensions for Dynamic Time Warping

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international conference on hardware/software codesign and system synthesis (codes)

作者： Joseph Tarango Eamonn Keogh Philip Brisk Department of Compuer Science and Engineering University of California Riverside Riverside CA

ISBN: (纸本)9781479914173

Processor specialization through application-specific instruction set customization can significantly improve performance while reducing energy. Due to the costs associated with semiconductor fabrication, specialized processors are only viable for products with high production volumes. The emergence of low-cost sensor-based computing products in recent years has created an urgent need to process time-series data with the utmost efficiency. Although most sensor data is fixed-point, the normalization process-an absolute necessity for highly accurate similarity search of time-series data-converts the data to floating-point in order to avoid a loss in precision. The sensors that collect time-series data are typically connected to low-power microcontrollers or RISC processors sans floating point units. The computational requirements of real-time similarity search would overwhelm such processors. To address this concern, we introduce a specialized instruction set for time-series data mining applications to a 32-bit embedded processor, yielding a 4.87x performance improvement and a 78% reduction in energy consumption compared to a highly optimized software implementation.

关键词： Time complexity Time series analysis Real-time systems Data mining Robot sensing systems Heuristic algorithms software

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Improving polyhedral code generation for high-level synthesis 13

Improving polyhedral code generation for high-level synthesi...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Wei Zuo Peng Li Deming Chen Louis-Noël Pouchet Shunan Zhong Jason Cong Beijing Institute of Technology PKU/UCLA Joint Research Institution for Science and Engineering University of Illinois at Urbana-Champaign University of California Los Angeles

ISBN: (纸本)9781479914173

High-level synthesis (HLS) tools are now capable of generating high-quality RTL codes for a number of programs. Nevertheless, for best performance aggressive program transformations are still required to exploit data reuse and enable communication/computation overlap. The polyhedral compilation framework has shown great promise in this area with the development of HLS-specific polyhedral transformation techniques and tools. However, all these techniques rely on polyhedral code generation to translate a schedule for the program's operations into an actual C code that is input to the HLS tool. In this work we study the changes to the state-of-the-art polyhedral code generator CLooG which are required to tailor it for HLS purposes. In particular, we develop various techniques to significantly improve resource utilization on the FPGA. We also develop a complete technique geared towards effective code generation of rectangularly tiled code, leading to further improvements in resource utilization. We demonstrate our techniques on a collection of affine benchmarks, reducing by 2x on average (up to 10x) the area used after high-level synthesis.

关键词： Field programmable gate arrays Optimization Tiles Benchmark testing Table lookup Digital signal processing Measurement

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pvFPGA: Accessing an FPGA-based hardware accelerator in a paravirtualized environment 13

pvFPGA: Accessing an FPGA-based hardware accelerator in a pa...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Wei Wang Miodrag Bolic Jonathan Parri Computer Architecture Research Group University of Ottawa Ottawa Ontario Canada

ISBN: (纸本)9781479914173

In this paper we present pvFPGA, the first system design solution for virtualizing an FPGA-based hardware accelerator on the x86 platform. Our design adopts the Xen virtual machine monitor (VMM) to build a paravirtualized environment, and a Xilinx Virtex-6 as an FPGA accelerator. The accelerator communicates with the x86 server via PCI Express (PCIe). In comparison to the recent accelerator virtualization solutions which primarily intercept and redirect API calls to the hosted or privileged domain's user space, pvFPGA virtualizes an FPGA accelerator directly at the lower device driver level. This gives rise to higher efficiency and lower overhead. In pvFPGA, each unprivileged domain allocates a shared data pool for both user-kernel and inter-domain data transfer. In addition, we propose a new component, the coprovisor, which enables multiple domains to simultaneously access an FPGA accelerator. The experimental results have shown that 1) pvFPGA achieves close-to-zero overhead compared to accessing the FPGA accelerator without the VMM layer, 2) the FPGA accelerator is successfully shared by multiple domains, and 3) distributing different maximum data transfer bandwidths to different domains is achieved by regulating the size of the shared data pool at the split driver loading time.

关键词： Field programmable gate arrays hardware Kernel Virtualization Servers Virtual machine monitors Aerospace electronics

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Dimensioning and configuration of EES systems for electric vehicles with boundary-conditioned adaptive scalarization 13

Dimensioning and configuration of EES systems for electric v...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Wanli Chang Martin Lukasiewycz Sebastian Steinhorst Samarjit Chakraborty TUM CREATE Singapore TU Munich Germany

ISBN: (纸本)9781479914173

Electric vehicles (EVs) are widely considered as a solution for efficient, sustainable and intelligent transportation. An electrical energy storage (EES) system is the most important component in an EV in terms of performances and cost. This work proposes an approach for optimal dimensioning and configuration of EES systems in EVs. It is challenging to find optimal design points in the parameter space, which expands exponentially with the number of battery types available and the number of cells that can be implemented for each type. A multi-objective optimization problem is formulated with the driving range, rated power output, installation space and cost as design targets. We report a novel boundary-conditioned adaptive scalarization technique to solve both convex and concave problems. It provides a Pareto surface of evenly distributed Pareto points, presents the group of Pareto points according to different specific requirements from automotive manufacturers and also takes the fact in EES system design into account that the importance of an objective could be nonlinear to its value. Numerical and practical experiments prove that our proposed approach is effective for industry use and produces optimal solutions.

关键词： Batteries Optimization Mathematical model Vehicles Equations Linear programming system analysis and design

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On the automatic generation of GPU-oriented software applications from RTL IPs 13

On the automatic generation of GPU-oriented software applica...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Nicola Bombieri Franco Fummi Sara Vinco Dipartimento di Informatica Università di Verona Italy

ISBN: (纸本)9781479914173

Graphics processing units (GPUs) have been explored as a new computing paradigm for accelerating computation intensive applications. In particular, the combination between GPUs and CPU has proved to be an effective solution for accelerating the software execution, by mixing the few CPU cores optimized for serial processing with many smaller GPU cores designed for massively parallel computations. In addition, sustained by the need of low power consumption besides high performance, a recent trend is combining GPUs and CPU onto a single die (e.g., AMD Fusion, Intel Sandy Bridge, NVIDIA Tegra). The good tradeoff between computing capability and power consumption makes the integrated GPUs a promising alternative for accelerating a wide range of software application for embedded systems. Nevertheless, algorithms must be redesigned to take advantage of these architectures and such a manual parallelization often results in being unsatisfactory. This paper presents a methodology to automatically generate software applications for GPUs, by reusing existing and preverified register-transfer level (RTL) intellectual-properties (IPs). The methodology aims at exploiting the intrinsic parallelism of RTL IPs (such as process concurrency and pipeline micro-architecture) for generating the parallel software implementation of the functionality. The experimental results show how the performance obtained by running the RTL functionality as software applications on GPUs outperform those provided by the RTL code mapped into a hardware accelerator.

关键词： Graphics processing units Parallel processing Pipelines IP networks Instruction sets Computer architecture

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IVaM: Implicit variant modeling and management for automotive embedded systems 13

IVaM: Implicit variant modeling and management for automotiv...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Sebastian Graf Michael Glaß Dominic Wintermann Jürgen Teich Christoph Lauer University of Erlangen-Nuremberg Germany Friedrich-Alexander-Universitat Erlangen-Nurnberg Erlangen Bayern DE AUDI AG Ingolstadt Germany

ISBN: (纸本)9781479914173

In this paper, we propose a graph-based approach for the modeling and efficient analysis of functional variants of a car's electric and electronic (E/E) architecture functionality by combining local technical expert knowledge with global business knowledge. Starting with a variants system specification including a set of task graphs, linear constraints on binary variables are specified for their alternative selection as well as the selection of groups of alternatives called application groups. These constraints may stem from a certain domain knowledge, e. g., entertainment or power train domain, or global constraints. The typically vast space of resulting possible combinations of different selections of alternative behaviors will be termed variant space and those satisfying the set of formulated constraints valid variants. An important result of this paper is that the set of variants, and especially the set of valid variants, do not need to be modeled or stored explicitly but rather implicitly. Nevertheless do we show that using state-of-the-art PB solver techniques, we may determine the set of valid variants very efficiently. Each of these valid variants may subsequently be used as a candidate for design space exploration (DSE) in order to optimize also the mapping of the corresponding task graph functionalities to a final optimized E/E architecture. A real-world case study is provided to demonstrate the capabilities and efficiency of the presented approach on implicit variant modeling and analysis.

关键词： Space exploration Computer architecture hardware software Automotive engineering Business Sensors

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Designing a residential hybrid electrical energy storage system based on the energy buffering strategy 13

Designing a residential hybrid electrical energy storage sys...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Di Zhu Siyu Yue Yanzhi Wang Younghyun Kim Naehyuck Chang Massoud Pedram University of Southern California CA USA Seoul National University Korea

ISBN: (纸本)9781479914173

Due to severe variation in load demand over time, utility companies generally raise electrical energy price during periods of high load demand. A grid-connected hybrid electrical energy storage (HEES) system can help residential users lower their electric bills by storing energy during low-price hours and releasing the stored energy during high-price hours. A HEES system consists of different types of electrical energy storage (EES) elements, utilizing the benefits of each type while hiding their weaknesses. This paper presents a residential energy management system to maximize the annual profits on residential electric bills, based on a HEES system comprised of a lead-acid battery bank as the main storage bank and a Li-ion battery bank as the energy buffer. We first derive the optimal daily energy management policy based on energy buffering to minimize the daily energy cost. Next, we find the near-optimal design specifications of the energy management system, aiming at maximizing the amortized annual profits under practical constraints. We show that this system achieves averagely 11.10% more profits compared to the none-buffering HEES system.

关键词： Batteries Lead Discharges (electric) Pricing Energy management Supercapacitors

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VarEMU: An emulation testbed for variability-aware software 13

VarEMU: An emulation testbed for variability-aware software

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international conference on hardware/software codesign and system synthesis (codes)

作者： Lucas Wanner Salma Elmalaki Liangzhen Lai Puneet Gupta Mani Srivastava University of California Los Angeles

ISBN: (纸本)9781479914173

Modern integrated circuits, fabricated in nanometer technologies, suffer from significant power/performance variation across-chip, chip-to-chip and over time due to aging and ambient fluctuations. Furthermore, several existing and emerging reliability loss mechanisms have caused increased transient, intermittent and permanent failure rates. While this variability has been typically addressed by process, device and circuit designers, there has been a recent push towards sensing and adapting to variability in the various layers of software. Current hardware platforms, however, typically lack variability sensing capabilities. Even if sensing capabilities were available, evaluating variability-aware software techniques across a significant number of hardware samples would prove exceedingly costly and time consuming. We introduce VarEMU, an extension to the QEMU virtual machine monitor that serves as a framework for the evaluation of variability-aware software techniques. VarEMU provides users with the means to emulate variations in power consumption and in fault characteristics and to sense and adapt to these variations in software. Through the use (and dynamic change) of parameters in a power model, users can create virtual machines that feature both static and dynamic variations in power consumption. Faults may be injected before or after, or completely replace the execution of any instruction. Power consumption and susceptibility to faults are also subject to dynamic change according to an aging model. A software stack for VarEMU features precise control over faults and provides virtual energy monitors to the operating system and processes. This allows users to precisely quantify and evaluate the effects of variations on individual applications. We show how VarEMU tracks energy consumption according to variation-aware power and aging models and give examples of how it may be used to quantify how faults in instruction execution affect applications.

关键词： hardware Aging Integrated circuit modeling Registers Switching circuits Program processors

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