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检索条件"任意字段=2014 International Conference on Hardware/Software Codesign and System Synthesis, CODES ISSS 2014"

共 593 条记录，以下是261-270 订阅

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A variability-aware OpenMP environment for efficient execution of accuracy-configurable computation on shared-FPU processor clusters 13

A variability-aware OpenMP environment for efficient executi...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Abbas Rahimi Andrea Marongiu Rajesh K. Gupta Luca Benini Department of Computer Science and Engineering UC San Diego La Jolla CA USA Dipartimento di Ingegneria dell'Energia Elettrica e dell'lnformazione Universita di Bologna Bologna Italy

ISBN: (纸本)9781479914173

We propose a tightly-coupled, multi-core cluster architecture with shared, variation-tolerant, and accuracy-reconfigurable floating-point units (FPUs). The resilient shared-FPUs dynamically characterize FP pipeline vulnerability (FPV) and expose it as metadata to a software scheduler for reducing the cost of error correction. To further reduce this cost, our programming and runtime environment also supports controlled approximate computation through a combination of design-time and runtime techniques. We provide OpenMP extensions (as custom directives) for FP computations to specify parts of a program that can be executed approximately. We use a profiling technique to identify tolerable error significance and error rate thresholds in error-tolerant image processing applications. This information guides an application-driven hardware FPU synthesis and optimization design flow to generate efficient FPUs. At runtime, the scheduler utilizes FPV metadata and promotes FPUs to accurate mode, or demotes them to approximate mode depending upon the code region requirements. We demonstrate the effectiveness of our approach (in terms of energy savings) on a 16-core tightly-coupled cluster with eight shared-FPUs for both error-tolerant and general-purpose error-intolerant applications.

关键词： Pipelines Timing Approximation methods Registers Computer architecture Runtime software

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2010 IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, codes+isss 2010

2010 IEEE/ACM/IFIP International Conference on Hardware/Soft...

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8th IEEE/ACM international conference on hardware/software-Co-Design and system synthesis, codes+isss 2010

ISBN: (纸本)9781605589053

The proceedings contain 40 papers. The topics discussed include: embedded market: challenges and opportunities;rank based dynamic voltage and frequency scaling for tiled graphics processors;intermediate fabrics: virtual architectures for circuit portability and fast placement and routing;an elastic software cache with fast prefetching for motion compensation in video decoding;verification of dynamically reconfigurable embedded systems by model transformation rules;hardware/software optimization of error detection implementation for real-time embedded systems;scheduling garbage collection in real-time systems;hardware/software co-design for high performance computing: challenges and opportunities;optimal synthesis of latency and throughput constrained pipelined MPSOCs targeting streaming applications;power aware SID-based simulator for embedded multicore DSP subsystems;and accurate online power estimation and automatic battery behavior based power model generation for smartphones.

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2010 IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, codes+isss 2010: Foreword

2010 IEEE/ACM/IFIP International Conference on Hardware/Soft...

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2010 IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, codes+isss 2010 2010年 iii页

作者： Givargis, Tony Donlin, Adam

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software Energy Optimization Through Fine-Grained Function-Level Voltage and Frequency Scaling 12

Software Energy Optimization Through Fine-Grained Function-L...

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10th ACM international conference on hardware/software-codesign and system synthesis

作者： Brandolese, Carlo Fornaciari, William Politecn Milan I-20133 Milan Italy

ISBN: (纸本)9781450314268

This paper presents a methodology and a toolchain to perform estimation and optimization of the energy consumption associated to software execution on tiny embedded systems. The estimation phase is based on an ISA-level characterization of the target processor, while the optimization phase is made combining the estimation process with design space exploration in order to exploit fine-grained dynamic voltage and frequency scaling. The proposed approach operates at compile-time, with the granularity of single C functions and almost automatically augments the source code.

关键词： Power Optimization Embedded systems

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Fast Online synthesis of Generally Programmable Digital Microfluidic Biochips 12

Fast Online Synthesis of Generally Programmable Digital Micr...

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10th ACM international conference on hardware/software-codesign and system synthesis

作者： Grissom, Daniel Brisk, Philip Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA

ISBN: (纸本)9781450314268

We introduce an online synthesis flow for digital microfluidic biochips, which will enable real-time response to errors and control flow. The objective of this flow is to facilitate fast assay synthesis while minimally compromising the quality of results. In particular, we show that a virtual topology, which constrains the allowable locations of assay operations such as mixing, dilution, sensing, etc., in lieu of traditional placement, can significantly speed up the synthesis process without significantly lengthening assay execution time.

关键词： Microfluidics Laboratory-on-Chip (LoC) Electrowetting-on-Dielectric (EWoD) synthesis

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synthesis of Optimized hardware Transactors from Abstract Communication Specifications 12

Synthesis of Optimized Hardware Transactors from Abstract Co...

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10th ACM international conference on hardware/software-codesign and system synthesis

作者： Lee, Dongwook Park, Hyungman Gerstlauer, Andreas Univ Texas Austin Austin TX 78712 USA

ISBN: (纸本)9781450314268

Increasing system complexity and heterogeneity make system integration and communication synthesis a growing concern. Even with transaction-level modeling and high-level synthesis of hardware, communication interfaces still have to be manually designed at a low protocol level. To address this challenge, we present a design flow for automatic synthesis of hardware transactors, which realize abstractly specified communication semantics OH top of protocol-level transactions. Transactor synthesis is tightly coupled with high-level synthesis of computation for integrated computation/communication co-design of complete hardware processors, thus establishing a seamless path from abstract system specifications down to hardware implementations in synthesizable RTL. The flow supports a generic set of communication semantics and target implementations, where transactors are custom-generated for a specific application and architecture combination. Furthermore, we develop protocol stack optimizations that reduce the area and performance overhead of synthesized communication interfaces. We have applied our synthesis flow to several industrial-strength examples under various communication settings. Results show that synthesized interfaces are comparable to manual designs in terms of area and latency, where protocol stack optimizations can reduce area and latency overhead by up to 77% and 21%, respectively.

关键词： transactor hardware synthesis interface synthesis

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A Case of system-level hardware/software Co-design and Co-verification of a Commodity Multi-Processor system with Custom hardware 12

A Case of System-level Hardware/Software Co-design and Co-ve...

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10th ACM international conference on hardware/software-codesign and system synthesis

作者： Hong, Sungpack Oguntebi, Tayo Casper, Jared Bronson, Nathan Kozyrakis, Christos Olukotun, Kunle Oracle Labs Belmont USA Stanford University Palo Alto USA

ISBN: (纸本)9781450314268

This paper presents an interesting system-level co-design and co-verification case study for a non-trivial design where multiple high-performing x86 processors and custom hardware were connected through a coherent interconnection fabric. In functional verification of such a system, we used a processor bus functional model (BFM) to combine native software execution with a cycle-accurate interconnect simulator and an HDL simulator. However, we found that significant extensions need to be made to the conventional BFM methodology in order to capture various data-race cases in simulation, which eventually happen in modern multi-processor systems. Especially essential were faithful imp lementations of the memory consistency model and cache coherence protocol, as well as timing randomization. We demonstrate how such a co-simulation environment can be constructed from existing tools and software. Lessons from our study can similarly be applied to design and verification of other tightly-coupled systems.

关键词： Co-Verification Co-Simulation Bus Functional Model FPGA Prototyping Transactional Memory

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Designing Parameterized Signal Processing IPs for High Level synthesis in a Model Based Design Environment 12

Designing Parameterized Signal Processing IPs for High Level...

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10th ACM international conference on hardware/software-codesign and system synthesis

作者： Butt, Shahzad Ahmad Lavagno, Luciano Politecn Torino Italy Elect & Telecommun Dept Corso Duca Abruzzi 24 Turin Italy

ISBN: (纸本)9781450314268

Model based hardware/software synthesis can lead to fast and efficient embedded system implementations, by enabling quick design space exploration. High level hardware modeling and implementation can be accelerated by using functionally verified parameterized models that are optimized for high level hardware synthesis. Such models can be designed so that they can be easily integrated with a high level modeling environment, such as Simulink, and at the same time provide ample flexibility to perform design space exploration when mapped to hardware. During signal processing hardware design, the focus is mostly on the architectural representation (data parallelism, pipelining, memory access, etc.) to meet throughput requirement and on data path modeling to analyze the effects of quantization. In this paper we present our experience of modeling an FFT block that can be integrated with the Simulink model based design environment for simulation and verification, and later can be used to perform architectural design space exploration and hardware implementation with optimal data path selection. A key advantage of our model is that the very same bit-accurate C code is used for simulation and for high-level synthesis, because it has been written with both aspects in mind (while for software implementation either our code or the code provided by the Mathworks can be used equally well). To prove the feasibility of our proposed approach we synthesized our FFT for two DSP applications with very different performance and cost requirements, namely a frequency domain audio detector and a GPS acquisition algorithm, and compared it with existing manual implementations

关键词： Model-based design Model-based high level synthesis synthesis from Simulink models Parameterized IPs Design reuse Audio detector GPS acquisition C/C plus plus hardware IP description FFT

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Dynamic Property Mining for Embedded software 12

Dynamic Property Mining for Embedded Software

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10th ACM international conference on hardware/software-codesign and system synthesis

作者： Bonato, Marco Di Guglielmo, Giuseppe Fujita, Masahiro Fummi, Franco Pravadelli, Graziano Univ Verona Dept Comp Sci Str Grazie 15 I-37100 Verona Italy Univ Tokyo Japan Sci & Technol Agcy VLSI Design & Educ Ctr CREST Tokyo Japan

ISBN: (纸本)9781450314268

The importance of specification definition in the embedded-software design flow has been proven over the years. The entire design process relies on the specification quality, which inevitably depends on designer knowledge and skills. Automatic property mining is part of the efforts proposed to make this activity easier for the designers. Nonetheless, the existing approaches are limited to the detection of either arithmetic invariants of programs or temporal properties for Boolean designs, e.g., bit-level hardware descriptions. In this work, we present a dynamic mining approach able to infer linear temporal logic (LTL) properties for embedded software. The mined properties are in the form of temporal relationships between arithmetic expressions. The approach considers the execution traces only, thus it is completely independent from the code implementation. Experimental results demonstrate the effectiveness of the approach.

关键词： Temporal Property Dynamic Mining Embedded software

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DevScope: A Nonintrusive and Online Power Analysis Tool for Smartphone hardware Components 12

DevScope: A Nonintrusive and Online Power Analysis Tool for ...

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10th ACM international conference on hardware/software-codesign and system synthesis

作者： Jung, Wonwoo Kang, Chulkoo Yoon, Chanmin Kim, Dongwon Cha, Hojung Yonsei Univ Dept Comp Sci Seoul 120749 South Korea

ISBN: (纸本)9781450314268

Smartphone power modeling is an important technique for users, application developers, and hardware manufacturers to build energy-aware systems. Compared to traditional offline techniques that use external power measurement devices, the online approach uses a built-in BMU (Battery Monitoring Unit), which has the advantage of generating a dynamic power model. However, the very low update rate of a BMU is an issue for online power modeling. In this paper, we introduce an autonomous power modeling tool for smartphones called DevScope, which overcomes the limitations of BMU-based online power modeling. DevScope controls components according to the BMU update rate, and derives the component power model automatically by analyzing the changes of power state. With DevScope, we construct an online and automatic power modeling that reflects both the diversity of users' environments and smartphone hardware complexity. By evaluating the scheme with various smartphones and configurations, we show that DevScope, indeed, generates a flexible and accurate power model.

关键词： Smartphone Power Analysis Power Modeling Battery Monitoring Unit

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