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SPI-SNOOPER: A hardware-software Approach for Transparent Network Monitoring in Wireless Sensor Networks 12

SPI-SNOOPER: A Hardware-Software Approach for Transparent Ne...

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10th ACM international conference on hardware/software-codesign and system synthesis

作者： Hossain, Mohammad Sajjad Lee, Woo Suk Raghunathan, Vijay Google Inc Mountain View CA USA Purdue Univ W Lafayette IN 47907 USA

ISBN: (纸本)9781450314268

The lack of post-deployment visibility into system operation is one of the major challenges in ensuring reliable operation of remotely-deployed embedded systems such as wireless sensor nodes. Over the years, many software-based solutions (in the form of debugging tools and protocols) have been proposed for in-situ system monitoring. However, all of them share the trait that the monitoring functionality is implemented as software executing on the same embedded processor that the main application executes on. This is a poor design choice from a reliability perspective. This paper makes the case for a joint hardware-software solution to this problem and advocates the use of a dedicated reliability co-processor that is tasked with monitoring the operation of the embedded system. As an embodiment of this design principle, this paper presents SPI-SNOOPER, a co-processor augmented hardware platform specifically designed for network monitoring. SPI-SNOOPER is completely cross-compatible with the TELOS wireless sensor nodes from an operational standpoint and is based on a novel hardware architecture that enables transparent snooping of the communication bus between the main processor and the radio of the wireless embedded system. The accompanying software architecture provides a powerful tool for monitoring, logging, and even controlling all the communication that takes place between the main processor and the radio. We present a rigorous evaluation of our prototype and demonstrate its utility using a variety of usage scenarios.

关键词： Wireless sensor networks reliability hardware-software co-design co-processor monitoring snooping

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From RTL IP to Functional system-Level Models with Extra-Functional Properties 12

From RTL IP to Functional System-Level Models with Extra-Fun...

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10th ACM international conference on hardware/software-codesign and system synthesis

作者： Lorenz, Daniel Gruettner, Kim Bombieri, Nicola Guarnieri, Valerio Bocchio, Sara OFFIS Institute for Information Technology Oldenburg Germany University of Verona Verona Italy STMicroelectronics Agrate Brianza Italy

ISBN: (纸本)9781450314268

The paper presents a novel abstraction methodology for generating time- and power-annotated TLM models from synthesizable RTL descriptions. The proposed techniques allow the integration of existing RTL IP components into virtual platforms for early software development and platform design, configuration, and exploration. With the proposed approach, IP models can be natively integrated into systemC TLM-2.0 platforms and executed 10-1000 times faster compared to state-of-the-art RTL simulators. The abstraction methodology guarantees preservation of the behaviour and timing of the RTL models. Target technology dependent power properties of IP components are represented as power state-machines and integrated into the abstracted TLM models. The experimental results show a relative error less than 10% of the abstracted model's power consumption compared to state-of-the-art RTL power simulators. The evaluation has been performed on RTL IP components with different characteristics and demonstrates the effectiveness of the presented abstraction methodology.

关键词： HW/SW Timing and Power Simulation Virtual Prototypes RTL to TLM Abstraction

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The system Verification Methodology for advanced TLM verification 12

The System Verification Methodology for advanced TLM verific...

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10th ACM international conference on hardware/software-codesign and system synthesis, codes+isss 2012, Co-located with 8th Embedded systems Week, ESWEEK 2012

作者： Oliveira, Marcio F.S. Haedicke, Finn Drechsler, Rolf Kuznik, Christoph Le, Hoang M. Ecker, Wolfgang Mueller, Wolfgang Große, Daniel Esen, Volkan C-LAB University of Paderborn 33102 Paderborn Germany Institute of Computer Science University of Bremen 28359 Bremen Germany Cyber-Physical Systems DFKI GmbH 28359 Bremen Germany Infineon Technologies AG 85579 Neubiberg Germany

ISBN: (纸本)9781450314268

The IEEE-1800 systemVerilog [20] system description and verification language integrates dedicated verification features, like constraint random stimulus generation and functional coverage, which are the building blocks of the Universal Verification Methodology (UVM) [3], the emerging standard for electronic systems verification. In this article, we introduce our system Verification Methodology (SVM) as a systemC library for advanced Transaction Level Modeling (TLM) testbench implementation. As such, we first present systemC libraries for the support of verification features like functional coverage and constrained random stimulus generation. Thereafter, we introduce the SVM with advanced TLM support based on systemC and compare it to UVM and related approaches. Finally, we demonstrate the application of our SVM by means of a testbench for a two wheel self-balancing electric vehicle. Copyright 2012 ACM.

关键词： Automobile electronic equipment

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The Roce-Bush Router: A Case for Routing-centric Dimensional Decomposition for Low-latency 3D NoC Routers 12

The Roce-Bush Router: A Case for Routing-centric Dimensional...

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10th ACM international conference on hardware/software-codesign and system synthesis

作者： Salas, Miguel Pasricha, Sudeep Intel Corp Ft Collins CO USA Colorado State Univ Dept Elect & Comp Engn Ft Collins CO 80523 USA

ISBN: (纸本)9781450314268

As 3D system-On-Chips (SoCs) come ever closer to becoming the standard for high performance ICs, 3D Networks on Chips (NoCs) have emerged as a key component in meeting performance constraints and ensuring power-efficiency. Among the proposed 3D router architectures, dimensionally-decomposed routers are widely accepted as an efficient solution to deal with the increased port count and the accompanying exponential power and area increases. All decompositions proposed thus far have however been dimensionally static, that is, they have set in stone a particular bias among the three dimensions. This paper presents a novel router with a routing-centric decomposition and virtual channel buffer sharing called the Roce-Bush router. To our knowledge, this is the first work that integrates routing-awareness in the context of dimensional decomposition and buffer resource allocation for NoC routers. Experimental results involving RTL level implementations of our router and synthesis at 45nm show that compared to a dimensional-agnostic decomposed router, the Roce-Bush router can achieve up to 14% better performance and 5% lower power.

关键词： Network-on-chips NoCs system-on-chips 3D ICs router architecture

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A Testbench Specification Language for systemC Verification 12

A Testbench Specification Language for SystemC Verification

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10th ACM international conference on hardware/software-codesign and system synthesis

作者： Di Guglielmo, Giuseppe Pravadelli, Graziano Univ Verona I-37100 Verona Italy

ISBN: (纸本)9781450314268

Testing of embedded systems, operating in the real environment, is generally performed by using an industrial test bench that stimulates the system through sensors and human-machine interfaces. The test bench provides the engineers with a set of tools for reproducing the environmental conditions which may affect the system. On the contrary, a different approach is adopted at the early stages of the design flow, when system level languages, like systemC, are used to describe the functionality of the design. At this level, stimuli for testing the design are traditionally generated in a random or statistical way, which makes more difficult to capture well-specific behaviors of the considered environment, thus decreasing the effectiveness and the efficiency of the verification. This is particularly evident for dynamic assertion-based verification where, to avoid vacuous passes of assertions, stimuli must reflect specific scenarios to activate the assertions. In this work, we propose a graphical framework to automatically generate stimuli, particularly suited to be used for dynamic ABV of embedded SW. The framework relies on the definition of a Testbench Specification Language (TSL) that allows to formally capture the behavior of the real environment where embedded SW is intended to be executed, i.e., how input values evolve on time intervals. Then, the framework allows to automatically synthesize TSL descriptions into systemC-based stimuli generators, which exploit and extend the functionality of the systemC Verification Library.

关键词： Testbench Specification Language Embedded software Stimuli Generation systemC Verification Library

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A Real-Time, Energy-Efficient system software Suite for Heterogeneous Multicore Platforms 12

A Real-Time, Energy-Efficient System Software Suite for Hete...

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10th ACM international conference on hardware/software-codesign and system synthesis

作者： Hung, Shih-Hao Shih, Chi-Sheng Kuo, Tei-Wei Tu, Chia-Heng Chang, Che-Wei Natl Taiwan Univ Grad Inst Networking & Multimedia Taipei 106 Taiwan Natl Taiwan Univ Dept Comp Sci & Informat Engn Taipei 106 Taiwan

ISBN: (纸本)9781450314268

Heterogeneous multicore systems have become the trend for the embedded market due to its advantage of power/performance over traditional designs. However, monitoring the workload, scheduling the tasks, and managing the energy consumption to enable energy-efficient, real-time applications are increasingly challenging on such systems as both the applications and systems become complex. In this paper, we introduce a comprehensive approach to address the key problems and accelerate the design of a heterogeneous multicore embedded system by providing a suite of energy-aware system software with tightly coupled real-time support and performance/power modeling facilities. We start with a rapid full system modeling/simulation framework to characterize the application workload, design energy-saving algorithms, and verify if performance requirements are met by hardware specifications during the early design stage. With special considerations on today's multicore embedded systems, we developed several key components and integrated them as a system software suite: a portable, efficient library to support inter-core communications and multicore programming, a lightweight kernel for dynamically monitoring and sharing the workload among the processor cores, and a dynamic voltage and frequency scaling scheme to adjust the setting of the processors to save energy. The system software has been implemented on the PAC Duo system as a case study, with experimental results to demonstrate the effectiveness of the proposed approach. This paper discusses the novel techniques included in this system software and shares the lessons that we have learned from this work.(1)

关键词： Multicore emulator inter-core communication library load sharing kernel energy saving algorithm

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Automatic Extraction of Multi-Objective Aware Pipeline Parallelism Using Genetic Algorithms 12

Automatic Extraction of Multi-Objective Aware Pipeline Paral...

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10th ACM international conference on hardware/software-codesign and system synthesis

作者： Cordes, Daniel Engel, Michael Marwedel, Peter Neugebauer, Olaf TU Dortmund Univ Dortmund Germany Informat Centrum Dortmund EV Dortmund Germany

ISBN: (纸本)9781450314268

The development of automatic parallelization techniques has been fascinating researchers for decades. This has resulted in a significant amount of tools, which should relieve the designer from the burden of manually parallelizing an application. However, most of these tools only focus on minimizing execution time which drastically reduces their applicability to embedded devices. It is essential to find good trade-offs between different objectives like, e.g., execution time, energy consumption, or communication overhead, if applications should be parallelized for embedded multiprocessor system-on-chip (MPSoC) devices. Another important aspect which has to be taken into account is the streaming-based structure found in many embedded applications such as multimedia and network services. The best way to parallelize these applications is to extract pipeline parallelism. Therefore, this paper presents the first multi-objective aware approach exploiting pipeline parallelism automatically to make it most suitable for resource-restricted embedded devices. We have compared the new pipeline parallelization approach to an existing task-level extraction technique. The evaluation has shown that the new approach extracts very efficient multi-objective aware parallelism. In addition, the two approaches have been combined and it could be shown that both approaches perfectly complement each other.

关键词： Automatic Parallelization Embedded software Genetic Algorithms Multi-Objective Pipeline Parallelism Energy

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synthesis of Custom Networks of Heterogeneous Processing Elements for Complex Physical system Emulation 12

Synthesis of Custom Networks of Heterogeneous Processing Ele...

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10th ACM international conference on hardware/software-codesign and system synthesis

作者： Huang, Chen Miller, Bailey Vahid, Frank Givargis, Tony Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA Univ Calif Irvine Ctr Embedded Comp Syst Irvine CA USA

ISBN: (纸本)9781450314268

Physical system models that consist of thousands of ordinary differential equations can be synthesized to field-programmable gate arrays (FPGAs) for highly-parallelized, real-time physical system emulation. Previous work introduced synthesis of custom networks of homogeneous processing elements, consisting of processing elements that are either all general differential equation solvers or are all custom solvers tailored to solve specific equations. However, a complex physical system model may contain different types of equations such that using only general solvers or only custom solvers does not provide all of the possible speedup. We introduce methods to synthesize a custom network of heterogeneous processing elements for emulating physical systems, where each element is either a general or custom differential equation solver. We show average speedups of 45x over a 3 GHz single-core desktop processor, and of 11x and 20x over a 3 GHz four-core desktop and a 763 MHz NVIDIA graphical processing unit, respectively. Compared to a commercial high-level synthesis tool including regularity extraction, the networks of heterogeneous processing elements were on average 10.8x faster. Compared to homogeneous networks of general and single-type custom processing elements, heterogeneous networks were on average 7x and 6x faster, respectively.

关键词： Real-time emulation field-programmable gate array (FPGA) ordinary differential equation (ODE) solving physical models cyber-physical systems differential equation synthesis high-level synthesis system-level synthesis processing elements

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A MDD Methodology for Specification of Embedded systems and Automatic Generation of Fast Configurable and Executable Performance Models 12

A MDD Methodology for Specification of Embedded Systems and ...

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10th ACM international conference on hardware/software-codesign and system synthesis

作者： Herrera, Fernando Posadas, Hector Penil, Pablo Villar, Eugenio Ferrero, Francisco Valencia, Raul Univ Cantabria ETSIIT Av Castros Sn Santander Santander 39009 Spain SAU GMV Aerosp & Def E-28760 Tres Cantos Spain

ISBN: (纸本)9781450314268

This paper presents the COMPLEX UML/MARTE modeling methodology and its related framework for automatic generation of executable performance models. The modeling methodology supports Model-Driven Development (MDD), required by industrial flows, and a novel set of modeling features specifically suitable for Design Space Exploration (DSE), a crucial design activity. The COMPLEX framework has other advantages for DSE. The COMPLEX tooling enables the automatic generation of an executable and configurable model for fast performance analysis without requiring engineering effort. The COMPLEX tooling automates the production of an easily portable text-based representation of the UML/MARTE model. This representation is read by the underlying simulation infrastructure, which automatically builds a fast performance model supporting the evaluation of different configurations of the system. An important aspect of this performance analysis framework is that it supports a system-level text-based front-end, which is produced from the COMPLEX UML/MARTE model, and which avoids the development of SW implementations, HW refinements, or the implementation of HW/SW interfaces. Moreover, neither code regeneration, nor recompilation is required for any DSE iterations, and thus, the time taken in the exploration is mostly due to model simulation.

关键词： Electronic system-Level (ESL) Design Space Exploration (DSE) Model-Driven Development (MDD) Component-Based Design (CBD) UML MARTE systemC

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HyCoS: Hybrid Compiled Simulation of Embedded software with Target Dependent Code 12

HyCoS: Hybrid Compiled Simulation of Embedded Software with ...

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10th ACM international conference on hardware/software-codesign and system synthesis

作者： Wang, Zhonglei Henkel, Joerg Karlsruhe Inst Technol Chair Embedded Sytems D-76131 Karlsruhe Germany

ISBN: (纸本)9781450314268

Source-Level Simulation (SLS) has become a de-facto standard technique for fast simulation of embedded software. The basic idea of SLS is to generate software simulation models by annotating low-level timing information in to application source code. The obtained source-level simulation models provide a good alternative to traditional Instruction Set Simulators (ISS) for system-level design space exploration of complex embedded systems. However, the generation of source-level simulation models requires the source code to be available, and therefore, it is not applicable to software that contains target dependent code (e.g. inline assembler and pre-compiled library functions). Since target dependent code is often used in embedded software development, this problem strongly limits the applicability of SLS. To overcome this limitation, we propose for the first time a novel hybrid compiled simulation approach called HyCoS that takes advantage of SLS and provides support for target dependent code by incorporating an instruction-level compiled simulation technique. A major challenge to be addressed in the hybrid simulation is the implementation of synchronization and communication between code simulated at different abstraction levels, in order to achieve functional correctness. In addition, it is also crucial to improve estimation accuracy. In this paper we present novel methods for these goals. Experimental results show that, compared to an ISS, HyCoS achieves an average simulation speed of 464 MIPS on a normal desktop computer, 128.0x faster than a standard ISS while achieving comparable accuracy. Even in comparison to fast instruction-level compiled simulation, it also achieves a speedup of up to 4.2x. We also use a multimedia application to demonstrate the efficiency of our approach that is especially beneficial in complex multiprocessor simulation.

关键词： Hybrid compiled simulation source-level simulation system level design embedded systems

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