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Highly-cited ideas in system codesign and synthesis 08

Highly-cited ideas in system codesign and synthesis

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Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, codes+isss 2008

作者： Vahid, Frank Givargis, Tony Department of Computer Science and Engineering University of California Riverside United States Center for Embedded Computer Systems UC Irvine United States Center for Embedded Computer Systems University of California Irvine United States

ISBN: (纸本)9781605584706

We conducted a study of citations of papers published between 1996 and 2006 in the codes and isss conferences, representing the hardware/software codesign and system synthesis community. Citations, meaning non-self-citations only, were considered from all papers known to Google Scholar, as well as only from subsequent codes/isss papers. We list the most-cited codes/isss papers of each year, summarizing their topics, and discussing common features of those papers. For comparison purposes, we also measured citations for the computer architecture community's ISCA and MICRO conferences, and for the field-programmable gate array community's FPGA and FCCM conferences. We point out several interesting differences among the citation patterns of the three communities. Copyright 2008 ACM.

关键词： Computer architecture

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You can catch more bugs with transaction level honey 08

You can catch more bugs with transaction level honey

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Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, codes+isss 2008

作者： Abramovici, Miron Goossens, Kees Vermeulen, Bart Greenbaum, Jack Stollon, Neal Donlin, Adam DAFCA NXP Greenhills Software United States HDL Dynamics Xilinx Research

ISBN: (纸本)9781605584706

In this special session we explore holistic approaches to hardware/software debug that use or integrate transaction level models (TLMs). We present several TLM-based approaches to system-level diagnostics, ranging from use of most popular transaction level modeling languages through to hybrid technologies that combine TLMs with other well known diagnostic tools like in-silicon trace logic. Copyright 2008 ACM.

关键词： Modeling languages

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Symbolic voter placement for dependability-aware system synthesis 08

Symbolic voter placement for dependability-aware system synt...

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Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, codes+isss 2008

作者： Reimann, Felix Glaß, Michael Lukasiewycz, Martin Keinert, Joachim Haubelt, Christian Teich, Jürgen Hardware-Software-Co-Design Department of Computer Science University of Erlangen Nuremberg Germany

ISBN: (纸本)9781605584706

This paper presents a system synthesis approach for dependable embedded systems. The proposed approach significantly extends previous work by automatically inserting fault detection and fault toleration mechanisms into an implementation. The main contributions of this paper are 1) a dependability-aware system synthesis approach that automatically performs a redundant task binding and placement of voting structures to increase both, reliability and safety, respectively, 2) an efficient dependability analysis approach to evaluate lifetime reliability and safety, and 3) results from synthesizing a Motion-JPEG decoder for an FPGA platform using the proposed system synthesis approach. As a result, a set of high-quality solutions of the decoder with maximized reliability, safety, performance, and simultaneously minimized resource requirements is achieved. Copyright 2008 ACM.

关键词： Fault detection

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A performance-oriented hardware/software partitioning for datapath applications 08

A performance-oriented hardware/software partitioning for da...

引用

Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, codes+isss 2008

作者： Frigerio, Laura Salice, Fabio Dip. di Elettronica e Informazione Politecnico di Milano Piazza Leonardo da Vinci Milano Italy

ISBN: (纸本)9781605584706

This article proposes a hardware/software partitioning method targeted to performance-constrained systems for datapath applications. Exploiting a platform based design, a Timed Petri Net formalism is proposed to represent the mapping of the application onto the platform, allowing to statically extract performance estimations in early phases of the design process and without the need of expensive simulations. The mapping process is generalized in order to allow an automatic exploration of the solution space, that identifies the best performance/area configurations among several application-architecture combinations. The method is evaluated implementing a typical datapath performance constrained system, i.e. a packet processing application. Copyright 2008 ACM.

关键词： Mapping

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hardware/software partitioning of floating point software applications to fixed-pointed coprocessor circuits 08

Hardware/software partitioning of floating point software ap...

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Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, codes+isss 2008

作者： Saldanha, Lance Lysecky, Roman Department of Electrical and Computer Engineering University of Arizona United States

ISBN: (纸本)9781605584706

While hardware/software partitioning has been shown to provide significant performance gains, most hardware/software partitioning approaches are limited to partitioning computational kernels utilizing integers or fixed point implementations. software developers often initially develop an application using built-in floating point representations and later convert the application to a fixed point representation - a potentially time consuming process. In this paper, we present a hardware/software partitioning approach for floating point applications that eliminates the need for developers to rewrite software applications for fixed point implementations. Instead, the proposed approach incorporates efficient, configurable floating point to fixed point and fixed point to floating point hardware converters at the boundary between the hardware coprocessors and memory. This effectively separates the system into a floating point domain consisting of the microprocessor and memory subsystem and a fixed point domain consisting of the partitioned hardware coprocessors, thereby providing an efficient and rapid method for implementing fixed point hardware coprocessors. Copyright 2008 ACM.

关键词： Coprocessor

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Specification and OS-based implementation of self-adaptive, hardware/software embedded systems 08

Specification and OS-based implementation of self-adaptive, ...

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Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, codes+isss 2008

作者： Eustache, Yvan Diguet, Jean-Philippe Université Européenne de Bretagne UBS LabSTICC Lorient France

ISBN: (纸本)9781605584706

This paper presents our solution for specifying and imple-menting self-adaptivness within an OS-based and reconfig-urable embedded system according to objectives such as qual-ity of service (QoS), performance or power consumption. More precisely, we detail our approach to separate, at runtime, application-specific decisions and hardware/software imple-mentation decisions at system level. The first ones are re-lated to the control of the efficiency of applications, they are specified in Local Configuration Managers (LCM) based on the knowledge of application engineers. The second ones are generic and address the choice between various hardware and software implementations according to observations of the gap between online measurements and objectives set by the user, these decisions are implemented in the Global Con-figuration Manager (GCM) as an adaptive close-loop model. We have designed a video tracking application on an FPGA to demonstrate the effectiveness of our solution, results are given for a system built around a NIOS soft-core with μCOS II RTOS and new services for managing hardware and soft-ware tasks transparently. Copyright 2008 ACM.

关键词： Embedded systems

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Slack analysis in the system design loop 08

Slack analysis in the system design loop

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Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, codes+isss 2008

作者： Venkataramani, Girish Goldstein, Seth C. ECE Department Carnegie Mellon University Pittsburgh PA United States School of Computer Science Carnegie Mellon University Pittsburgh PA United States

ISBN: (纸本)9781605584706

We present a system-level technique to analyze the impact of design optimizations on system-level timing dependencies. This technique enables us to speed up the design cycle by substituting, in the design the loop, the time-consuming simulation step with a fast timing update routine. As a result, we can significantly reduce the design time from on the order of hours/days to the order of seconds/minutes. The update algorithm is defined on the Transaction Level Model (TLM) and can be used by any design flow that invokes TLM-based optimizations. This algorithm has linear-time complexity in the program size and experimental results indicate that any loss of accuracy due to this technique is negligible (

关键词： systems analysis

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A time-predictable system initialization design for huge-capacity flash-memory storage systems 08

A time-predictable system initialization design for huge-cap...

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Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, codes+isss 2008

作者： Wu, Chin-Hsien Department of Electronic Engineering National Taiwan University of Science and Technology Taipei Taiwan

ISBN: (纸本)9781605584706

The capacity of flash-memory storage systems grows at a speed similar to many other storage systems. In order to properly manage the product cost, vendors face serious challenges in system designs. How to provide an expected system initialization time for huge-capacity flash-memory storage systems has become an important research topic. In this paper, a time-predictable system initialization design is proposed for huge-capacity flash-memory storage systems. The objective of the design is to provide an expected system initialization time based on a coarse-grained flash translation layer. The time-predictable analysis of the design is provided to discuss the relation between the size of main memory and the system initialization time. The system initialization time can be also estimated and predicted by the time-predictable analysis. Copyright 2008 ACM.

关键词： Flash memory

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Model checking systemC designs using timed automata 08

Model checking SystemC designs using timed automata

引用

Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, codes+isss 2008

作者： Herber, Paula Fellmuth, Joachim Glesner, Sabine Software Engineering for Embedded Systems Group Technical University of Berlin Germany

ISBN: (纸本)9781605584706

systemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify systemC designs. In this paper, we present an approach to overcome this problem by defining the semantics of systemC by a mapping from systemC designs into the well-defined semantics of UPPAAL timed automata. The informally defined behavior and the structure of systemC designs are completely preserved in the generated UPPAAL models. The resulting UPPAAL models allow us to use the UPPAAL model checker and the UPPAAL tool suite, including simulation and visualization tools. The model checker can be used to verify important properties such as liveness, deadlock freedom or compliance with timing constraints. We have implemented the presented transformation, applied it to two examples and verified liveness, safety and timing properties by model checking, thus showing the applicability of our approach in practice. Copyright 2008 ACM.

关键词： Semantics

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Combination of instruction set simulation and abstract RTOS model execution for fast and accurate target software evaluation 08

Combination of instruction set simulation and abstract RTOS ...

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Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, codes+isss 2008

作者： Krause, Matthias Englert, Dominik Bringmann, Oliver Rosenstiel, Wolfgang FZI Forschungszentrum Informatik Haid-und-Neu-Str. 10-14 76131 Karlsruhe Germany Universität Tübingen Sand 13 72076 Tübingen Germany

ISBN: (纸本)9781605584706

Instruction set simulation and real time operating system modeling have become important issues for the design of distributed embedded systems. This paper presents a holistic approach to simulate a distributed, embedded system that includes target software, processing units, and abstract RTOS within a virtual prototype environment. The processing unit is modeled by an ISS, which is embedded in a systemC environment to allow the integration into a platform model. In comparison to existing approaches, the RTOS is not directly running on the ISS but outsourced and replaced by an RTOS model. This step strongly reduces simulation time since the execution on the ISS is much more time consuming in contrast to the execution on the host processor. The results show the theoretical and measured performance gain depending on the RTOS scheduler and task switching. Copyright 2008 ACM.

关键词： Embedded systems

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